LG LM-X120HM Service Manual page 96

U0301-A
MT6739-SBS
PMU_IF DRAM_IF
L27 B1
SYSRSTB SYSRSTB EMI0_EXTR
[8]
WATCHDOG R28 F18
[8] WATCHDOG VREF_EMI0
[8] SRCLKENA0 L23
SRCLKENA0
[8,13] SRCLKENA1 L24
SRCLKENA1
[8] RTC32K_CK N23
RTC32K_CK
L25
[8] PWRAP_SPI0_CSN
PWRAP_SPI0_CSN
PWRAP_SPI0_CK N24
[8] PWRAP_SPI0_CK
[8] PWRAP_SPI0_MO K26
PWRAP_SPI0_MO
L26
[8] PWRAP_SPI0_MI PWRAP_SPI0_MI
[8] AUD_CLK_MISO P26
AUD_CLK_MISO
N26
[8] AUD_DAT_MISO0 AUD_DAT_MISO0
AUD_DAT_MISO1 R27
[3,8] AUD_DAT_MISO1
AUD_SYNC_MISO N27
[8] AUD_SYNC_MISO
P28
[8] AUD_CLK_MOSI
AUD_CLK_MOSI
AUD_DAT_MOSI0 P29
[3,8] AUD_DAT_MOSI0
[8] AUD_DAT_MOSI1 N25
AUD_DAT_MOSI1
N28
[8] AUD_SYNC_MOSI AUD_SYNC_MOSI
PLLs Test Pin
Y2
TESTMODE
GND JTAG
JTAG_TMS AA3
[19] JTMS
Y4
[19] JTAG_TCK JTCK
Y3
[19] JTAG_TDI JTDI
AA2
[19] JTAG_TDO JTDO
Y1
[19] RESET_IN JRSTN
NC
A1
NC
A29
NC
AG1
NC_3P0
AG29
NC_1P5
MT6739WW
AUX_IN0_NTC
[3]
Thermistor / To sense board level temperature
Distance to AP is 5~7mm and away form other heat resource 10mm~12mm
U0301-B
MT6739-SBS
SIM ABB_IF
AB28
[12] SIM1_SCLK
SIM1_SCLK
AA28
R0302 [12] SIM1_SIO SIM1_SIO
SIM1_SRST Y28
1 2 [12] SIM1_SRST
GND
[12] SIM2_SCLK AB26
36/1% SIM2_SCLK
[12] SIM2_SIO AC26
SIM2_SIO
VREF_EMI [6]
[12] SIM2_SRST AD26
SIM2_SRST
BPI
AC22
BPI_BUS17
AD24
BPI_BUS16
AC10
BPI_BUS15 BPI_BUS15
[16]
AC24
BPI_BUS14 BPI_BUS14
[16]
AE23
[12] BPI_BUS13 BPI_BUS13
AC21
BPI_BUS12
[15]
BPI_BUS11 AD23
BPI_BUS11
[14]
BPI_BUS10 AF24
BPI_BUS10
[12]
BPI_BUS9 AD9
BPI_BUS9
BPI_BUS8 AE8
[16] BPI_BUS8
BPI_BUS7 AD8
[15] BPI_BUS7
RF MIPI
BPI_BUS6 AB10
[15] BPI_BUS6
BPI_BUS5 AF8
[15]
BPI_BUS5
RFIC_MIPI0_SCLK
BPI_BUS4 AD10
[15] BPI_BUS4 RFIC_MIPI0_SDATA
AE11
[16] BPI_BUS3 BPI_BUS3 RFIC_MIPI1_SCLK
RFIC_MIPI1_SDATA
AE10
[16] BPI_BUS2 BPI_BUS2
RFIC_MIPI2_SCLK
AC9
[15] BPI_BUS1 BPI_BUS1 RFIC_MIPI2_SDATA
AC8
BPI_BUS0 RFIC_MIPI3_SCLK
[15] BPI_BUS0
RFIC_MIPI3_SDATA
RF BSI
AUX IN
AE21
RFIC0_BSI_EN RFIC0_BSI_EN
[13]
AF20
RFIC0_BSI_CK RFIC0_BSI_CK
[13]
AG21
[13] RFIC0_BSI_D0 RFIC0_BSI_D0
AG20
RFIC0_BSI_D1
[13] RFIC0_BSI_D1
AF21
RFIC0_BSI_D2
REF POWER
MT6739WW
VIO18_PMU
1
NTC0301
1%
2
GND
R0301
AA16 1 2
LTEX26M_IN PMIC_CLK_BB [8]
0
AD14 [13]
TX_BBIP LTE_TX_BB0_IP
AE14 LTE_TX_BB0_IN
TX_BBIN [13]
AG14
TX_BBQP LTE_TX_BB0_QP [13]
AF14
LTE_TX_BB0_QN
TX_BBQN [13]
AF18 LTE_PRX_BB0_IP
PRX_BB_IP [13]
AG18
PRX_BB_IN LTE_PRX_BB0_IN [13]
AF17 LTE_PRX_BB0_QP [13]
PRX_BB_QP
AG17 LTE_PRX_BB0_QN
PRX_BB_QN [13]
AD18
DRX_BB_IP LTE_DRX_BB0_IP [13]
AE18
DRX_BB_IN LTE_DRX_BB0_IN [13]
AE17 LTE_DRX_BB0_QP
DRX_BB_QP [13]
AD17
DRX_BB_QN LTE_DRX_BB0_QN [13]
AF15
DET_BBIP LTE_DET_BB0_IP
[13]
AG15
DET_BBIN LTE_DET_BB0_IN [13]
AD15
DET_BBQP LTE_DET_BB0_QP [13]
AE15
DET_BBQN LTE_DET_BB0_QN [13]
AC13
APC VRAMP_DCDC [15]
AG9
MIPI0_SCLK [14]
AG8
MIPI0_SDATA
[14]
AF10
MIPI1_SCLK [15]
AF9
MIPI1_SDATA [15]
AF25 VIO18_PMU
AG25
AF23
AG23
R0329
C0398 0.1uF
150K/1%
2 1
R0328
AC12
AUXIN2 CABLE_ID[3,12]
C0398¿¿½ü¹Ü½Å°Ú·Å
0
AD12 AUX_IN1_NTC
AUXIN1 [14]
AE12
AUXIN0 AUX_IN0_NTC [3]
R0340
GND
C0303
C0302
680K 1%
1.0uF 1.0uF
C0304¾¡Á¿¿¿½ü¹Ü½Å°Ú·Å
AF12 REFP GND
REFP GND
C0302¡¢C0303¾¡Á¿¿¿½ü¹Ü½Å°Ú·Å
C0304
AG12
AVSS_REFN
0.1uF
VIO18_PMU
GND
Schematic design notice of "03_MT6739_BB1" page.
Note 03-1: AUD_DAT_MOSI is JTAG feature in bootstrap.
AUD_DAT_MOSI0 Mode
LO Default
Aux Func. trap_MD_JTAG_AP_JTAG
HI
Note 03-2: ANT_SEL2 and AUD_DAT_MISO1 is storage booting feature in bootstrap.
ANT_SEL2 AUD_DAT_MISO1 Storage Booting
HI LO
HI HI
LO LO
LO HI
96
U0301-C
MT6739-SBS
CSI DSI
RCP U5
[11] RCP
V4
[11] RCN RCN
W4
[11] RDP0 RDP0
W3
[11] RDN0 RDN0
RDP1 W2
[11] RDP1
W1
[11] RDN1 RDN1
U4
RDP2
U3
RDN2
U2
RDP3
V2
RDN3
RCP_A P3
[11] RCP_A
R3
[11] RCN_A RCN_A
DISP_PWM
R5
[11] RDP0_A
RDP0_A
R6
[11] RDN0_A RDN0_A
[11] RDP1_A R4
RDP1_A
P4
[11] RDN1_A RDN1_A
P2
RDP2_A RDP2_A
[11]
R2
RDN2_A
[11] RDN2_A
T2
[11] RDP3_A RDP3_A
T1
[11] RDN3_A RDN3_A
M5
CMDAT0
M7
CMDAT1
M6
CMPCLK
R0325 TP0307
TP-0.3MM
AC2
[11] CAM_CLK0 CMMCLK0
R0326
0
M4
[11] CAM_CLK1 CMMCLK1
0
SPI
R0320
IDDIG IDDIG
CABLE_ID AE1
[3,12] SPI0_CS
0
AF1
[12] LCM_ID0 SPI0_CK
AE2
LCM_ID1 SPI0_MO
[12]
AD2
NCHGEN SPI0_MI
[7]
NSHDN AE5
[7] SPI1_CS
AE4
[11]
GPIO_LCM_BIAS_ENN SPI1_CK
AD5
[11] SPI1_MO
LCD_EXT_VDD_EN
AE3
SPI1_MI
I2S
AE25
[11] CAM_FLASH_EN I2S0_BCK
AE26
[11] CAM_TORCH_EN I2S0_LRCK
AG26
[9] GPIO_SPK_EN I2S0_DATA_IN
AF4
CAM_EXT_AVDD_EN I2S1_BCK
[11]
AG2
[11] CAM_RST0 I2S1_LRCK
AF3
[9] GPIO_HAC_EN I2S1_DO
CAM_PDN0 AF2
[11] I2S1_MCK
MT6739WW
VIO18_PMU VIO18_PMU
AUD_DAT_MOSI0 [3,8] AUD_DAT_MISO1 [3,8]
EMMC_NAND_BOOTING [4]
GND GND
Note: 03-1
Note: 03-2
[AUD_DAT_MOSI0 default status is LO]
Note
N/A
MD JTAG = CMDAT0/CMDAT1/CMPCLK/CMMCLK/CMMCLK1
[ANT_SEL2 default status is LO] [ AUD_DAT_MISO1 default status is LO]
TLC Boot
SLC Boot
eMMC Boot
N/A
T27 TCP [11]
TCP
U27
TCN [ 11]
TCN
T26
TDP0 TDP0 [11]
T25
TDN0 TDN0 [11]
U29 TDP1
TDP1 [11]
U28
TDN1 TDN1
[11]
V28
TDP2 TDP2 [11]
W28
TDN2 TDN2 [11]
U26 TDP3 [11]
TDP3
U25
TDN3 TDN3 [11]
R0311
1 2
T28
VRT
GND
1.5K
AE28
DISP_PWM [11]
AB23
LCM_RST LCM_RST [12]
AB24
DSI_TE DSI_TE [12]
<TITLE>
TITLE: REV: <REV>
03_MT6739_BB1
DOCUMENT NO.: SIZED: A1
DEPARTMENT: Hardware DEPT.
COMPANY:
3 20
DESIGNER: <DESIGNER> Last Saved Date: 2019/4/8 SHEET: OF