Changes To Switch Architecture Section; Theory Of Operation; Switch Architecture; Changes To Figure 50 - Analog Devices ADG5412BF Datasheet

Data Sheet

THEORY OF OPERATION

SWITCH ARCHITECTURE

Each channel of the ADG5412BF/ADG5413BF
parallel pair of N-channel diffused metal-oxide semiconductor
(NDMOS) and P-channel DMOS (PDMOS) transistors. This
construction provides excellent performance across the signal
range. The ADG5412BF/ADG5413BF
ard switches when input signals with a voltage between V
V are applied. For example, the on resistance is 10 Ω typically
DD
and the appropriate control pin, INx, controls the opening or
closing of the switch.
Additional internal circuitry enables the switch to detect over-
voltage inputs by comparing the voltage on the source or drain
pin with V and V . A signal is considered overvoltage if it
DD SS
exceeds the supply voltages by the voltage threshold, V
threshold voltage is typically 0.7 V, but can range from 0.8 V
(when operating at −40°C) down to 0.6 V at +125°C. See Figure 28
to see the change in V with operating temperature.
T
The maximum voltage that can be applied to any switch input is
+55 V or −55 V. When the device is powered using the single-
supply of 25 V or greater, the maximum signal level reduces
from −55 V to −40 V at V
DD
maximum rating. Construction of the process allows the channel
to withstand 80 V across the switch when it is opened. These
overvoltage limits apply whether the power supplies are present
or not.
ESD
PROTECTION
Sx
FAULT
DETECTOR
INx
Figure 49. Switch Channel and Control Function
When an overvoltage condition is detected on either the source pin
or drain pin, the switch is automatically opened regardless of the
digital logic state, INx. The source and drain pins both become
high impedance and ensure that no current flows through the
switch. In Figure 29, the voltage on the drain pin can be seen to
follow the voltage on the source pin until the switch has turned off
completely and the drain voltage discharges through the load. The
maximum voltage and the rate at which the output voltage dis-
charges is dependent on the load at the pin. The ADG5412F/
ADG5413F are pin-compatible devices that are overvoltage
protected on the source pin only, with ESD diodes on the drain
pin that limit the maximum voltage while the switch is opening.
consists of a
channels operate as stand-
. The
T
= 40 V to remain within the 80 V
ESD
PROTECTION
Dx
SWITCH FAULT
DRIVER DETECTOR
AND
During overvoltage conditions, the leakage current into and out
of the switch pins is limited to tens of microamperes. This limit
protects the switch and connected circuitry from over stresses as
well as restricting the current drawn from the signal source. When
an overvoltage event occurs, the channels undisturbed by the
overvoltage input continue to operate normally without
additional crosstalk.
and
SS
ESD Performance
The ADG5412BF/ADG5413BF
the human body model (HBM). ESD protection cells allow the
voltage at the pins to exceed the supply voltage. See Figure 49
for a switch channel overview.
Trench Isolation
In the ADG5412BF
(trench) is placed between the NDMOS and the PDMOS
transistors of each switch. Parasitic junctions, which occur between
the transistors in junction-isolated switches, are eliminated, and
the result is a switch that is latch-up immune under all
circumstances. These devices pass a JESD78D latch-up test of
±500 mA for 1 sec, which is the harshest test in the specification.
TRENCH
Rev. B | Page 25 of 28
ADG5412BF/ADG5413BF
has an ESD rating of 3 kV for
and ADG5413BF, an insulating oxide layer
NDMOS PDMOS
P-WELL N-WELL
BURIED OXIDE LAYER
HANDLE WAFER
Figure 50. Trench Isolation