Acqiris U5309A User Manual page 54

Acquisition card, 2 or 8 channels, 8-bit, 500 ms/s to 2 gs/s, dc to 500 ghz bandwidth, with real-time processing
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5.4   Multi-purpose inputs and outputs
Signal Logic Levels
The multi-purpose IO signals are 3.3 V CMOS compatible (5V Tolerant buffer). The levels shown in the
table below should be observed.
Direction
Input
Output
Table 5.6 - Logic levels.
As an Input
The input is high-impedance and will be pulled high if unconnected via an internal weak pull-up (42.2 k
pull-up resistor).
Figure 5.4 - Programmable IO schematic
As an Output
The high level output will typically give 1.6 V into 50 Ω. As can be seen in the diagram below, the 3.3 V
output buffer has a 50 Ω resistor in series. Therefore the available output high level voltage will depend
on the load applied. In the example below a 50 Ω termination will result in a nominal high level of 1.6 V.
(Vo = (Rload/(50 + Rload)) * 3.3).
Figure 5.5 - Output equivalent circuit.
54
Low level
< 0.8 V
In the range 0 to 0.8 V
High level
> 2.0 to 3.45 V
In the range 1.6 to 3.3 V
U5309A User's Manual

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