Acqiris U5309A User Manual page 48

Acquisition card, 2 or 8 channels, 8-bit, 500 ms/s to 2 gs/s, dc to 500 ghz bandwidth, with real-time processing
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5.2   Trigger modes and time-stamps
Figure 5.1 - Acquisition timeline depending on the trigger delay defined.
Trigger delay parameter
The amount of pre-trigger delay can be adjusted between 0 and 100% of the acquisition time window
(i.e. sampling interval x number of samples), whereas the post-trigger delay can be adjusted within the
time interval:
from 0 to (2
where block_size is 16.
Pre- or post-trigger delays are just different aspects of the same trigger positioning parameter:
The condition of 100% pre-trigger indicates that all data points are acquired prior to the trigger,
i.e. the trigger point is at the end of the acquired waveform.
The condition of 0% pre-trigger (which is identical to a post-trigger of 0%) indicates that all data
points are acquired immediately after the trigger, i.e. the trigger point is at the beginning of the
acquired waveform.
The condition of a non-zero post-trigger delay indicates that the data points are acquired after
the trigger occurs, at a time that corresponds to the post-trigger delay, i.e. the trigger point is
before the acquired waveform.
By definition post-trigger settings are a positive number and pre-trigger settings are a negative number.
Thus it is only natural that the software drivers treat pre- and post-trigger delays as a single parameter
in seconds that can vary between:
– NumberSamples * SamplingInterval (100% pre-trigger)
and + MaxPostTrigSamples * SamplingInterval (max post-trigger).
The ADC card hardware accepts pre- and post-trigger adjustments in increments of 16 samples.
48
32
– 1) * block_size (samples)
U5309A User's Manual

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