Texas Instruments 990 Operation Manual page 14

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945255-9701
Memory write protect is required in the 990 Prototyping System, and is implemented on the
990/4 memory expansion circuit card. A memory parity feature (which provides parity error
detection logic and an interrupt signal to the CPU) is standard in the 990 Prototyping System.
The hardware memory configuration is shown in figure 1-2. The numbers at the left are byte
addresses.
Chassis. The computer chassis is available in two configurations, one that holds 6 full-size cards
and one that holds 13 full-size cards. In addition, a table-top chassis mounting option is available
with the 6-s10t chassis. The power supply is located in the computer chassis.
1.2.2.2 Interrupt, XOP and Trap Vectors. This discussion covers the different types of vectors
and explains the power-up trap.
Vectors. Located in 990/4 memory are dedicated locations reserved for interrupt, XOP and trap
vectors. The interrupt and XOP vectors are available for the exclusive use of user programs,
except that one XOP may be used for executing supervisor calls. A vector is a two-word pair
providing the program counter and workspace for the service routine that handles an interrupt or
XOP.
Power-Up Trap_ The power-up interrupt traps through a vector at address zero or address
FFFC
16 ,
depending on a jumper wire implemented on the 990/4 CPU board. This allows more
flexible memory allocation for dedicated systems that do not have an operator panel. The 990
PrototypingSystem powers up through trap address FFFC
16'
Trap addresses are illustrated in figure 1-3.
1.2.2.3 733 ASR Data Terminal. The 733 ASR Data Terminal provides the communication link
between the user and the computer system. It is an automatic send-receive terminal, allowing
either automatic or manual entry of data and output of data under keyboard or remote control.
The major components of the terminal are the following:
• Keyboard
• Thermal printer
• Two magnetic tape cassette units
CPU ADDRESS SPACE {64K BYTES X 8 BITS
32K WORDS X 16 BITS
0000
003E
0040
INTERRUPT TRAP ADDRESSES
007E
0080
XOP TRAP ADDRESSES
,FFF~
J.
.
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CPU ADDRESSES REPRESENTED AS 4
HEX DIGITS (LSB ADDRESSES BYTE)
(A) 133068
Figure 1-3. Trap Addresses
1-4
NOTE:
LOCATIONS FFFC THROUGH
FFFF ARE THE VECTOR FOR
THE POWER-UP TRAP
THROUGH FFFC.
Digital Systems Division