STC STC12C5A Series Manual page 57

1 :=
Set the SPCLK as HIGH while the communication is kept idle. That implies the leading
edge of the clock is the falling edge, and the trailing edge is the falling rising edge.
CPHA := Clock Phase
0 := (default)
Data is driven when pin SS is low and changes on the trailing edge of SPCLK,
and is sampled on the leading edge. (This setting is only valid while SSIG==0.)
1 :=
Data is driven on the leading edge of SPCLK, and is sampled on the trailing edge.
{SPR1, SPR0} := SPI clock Rate selector
{0,0} := (default)
Set the clock rate of the SPI as the frequency of the clock source over 4.
{0,1} :=
Set the clock rate of the SPI as the frequency of the clock source over 16.
{1,0} :=
Set the clock rate of the SPI as the frequency of the clock source over 64. {1,1} :=
Set the clock rate of the SPI as the frequency of the clock source over 128.
There are two extra SFRs make relation with SPI application.
SFR: SPDAT (SPI Data register)
Read/Write
Default: 0000-0000
Bit 7 6
Name
The SFR SPDAT holds the data to be transmitted or the data received.
SFR: SPSTAT (SPI STATe register)
Read/Write
Default: 00XX-XXXX
Bit 7 6
SPIF WCOL
Name
SPIF := SPI transfer completion flag.
When a serial transfer finishes, the SPIF bit is set and an interrupt is generated if both the
ESPI(AUXR.3) bit and the EA(IE.7) bit are set. If SS is an input and is driven low when
SPI is in master mode with SSIG=0, SPIF will also be set to signal the "mode change".
The SPIF is cleared in software by "writing 1 to this bit".
WCOL := SPI Write Collision flag
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5 4
5 4
STC12C5Axx Technical Summary
Address: 0X86H
3 2 1
Address: 0X84H
3 2 1
0
0
57
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