Features - STC STC12C5A Series Manual

Features

Enhanced 80C51 Central Processing Unit
3.3V/5V operation voltage, built-in Low-Voltage Detector and Reset circuit
Operation frequency range up to 25MHz
Max 64K bytes on-chip flash memory with ISP/IAP capability
256 byte scratch-pad RAM and 1024 bytes of auxiliary RAM
Two-level code protection for flash memory access
Two 16-bit timer/counter
10 sources, 4-level-priority interrupt capability
Secondary UART2 with self baud-rate generator
One enhanced UART with automatic address recognition and frame error detection
SPI Master/Slave communication interface
15 bits Watch-Dog-Timer with 8-bit pre-scalar, one-time enabled
Two Channel Programmable Counter Array (PCA)
10-bit Analog-to-Digital Converter (ADC)
Power control: idle mode and power-down mode, Power-down can be woken-up through
INT0 and INT1
44(max) programmable I/O ports
Alternative built-in 6MHz oscillator
Fully static operation
Excellent noise immunity
Very low power consumption
Package type:
-PDIP-40:
-LQFP-44
-PQFP-44
-PLCC-44
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STC12C5Axx Technical Summary
3
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