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WM8960 Audio Board
I2S BUS
I2S has four signal lines, they are: SCLK, LRCK, SDATA and MCLK. And the first
three are most important. For better synchronize with system clock, you can mater
device clock, or external clock circuit.
Serial clock SCLK is also called as bit clock BCLK, which related to every bit of
digital audio. SCLK Frequency = 2 x Sample rate x Sample bits.
Frame clock LRCK (WS) is used to switch data of LEFT and RIGHT channels. If LRCK
is "1", it means that data of RIGHT channel are being transmitted, and LEFT channel
is active if LRCK is "0". The rate of LRCK is same as sample rate.
Serial data SDATA are audio data, they are binary complement.
Main clock (MCLK) is also called as System clock (Sys Clock), its frequency is 256
times or 384 times of sample rate. In order to support more function, we reserved the
MCLK interface of this module for more audio.
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