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Lattice Semiconductor OpenLDI/FPD-LINK/LVDS Manuals
Manuals and User Guides for Lattice Semiconductor OpenLDI/FPD-LINK/LVDS. We have
1
Lattice Semiconductor OpenLDI/FPD-LINK/LVDS manual available for free PDF download: User Manual
Lattice Semiconductor OpenLDI/FPD-LINK/LVDS User Manual (45 pages)
Receiver Interface IP
Brand:
Lattice Semiconductor
| Category:
Recording Equipment
| Size: 2 MB
Table of Contents
Table of Contents
2
1 Introduction
5
Quick Facts
5
Figure 1.1. Sample Openldi/Fpd-LINK/LVDS Receiver Interfaced to MIPI DSI System Diagram
5
Table 1.1. Openldi/Fpd-LINK/LVDS Receiver Interface IP Quick Facts
5
Features
6
Conventions
6
Nomenclature
6
Data Ordering and Data Types
6
Signal Names
6
Table 1.2. Openldi/Fpd-LINK/LVDS Receiver Interface IP Features Summary
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2 Functional Descriptions
7
Figure 2.1. Top Level Block Diagram
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Table 2.1. Openldi/Fpd-LINK/LVDS Receiver Interface IP Pin Function Description
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Figure 2.2. Openldi/Fpd-LINK/LVDS Input Bus Waveform
9
Interface and Timing Diagrams
9
Figure 2.3. Single Channel Openldi/Fpd-LINK/LVDS Input Bus Waveform for RGB888 Format
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Figure 2.4. Dual Channel Openldi/Fpd-LINK/LVDS Input Bus Waveform for RGB888 Format
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Figure 2.5. Single Channel Openldi/Fpd-LINK/LVDS Input Bus Waveform for RGB666 Format
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Figure 2.6. Dual Channel Openldi/Fpd-LINK/LVDS Input Bus Waveform for RGB666 Format
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Figure 2.7. Input to Output Waveform for Single Channel Openldi/Fpd-LINK/LVDS, Rx Gear 7
13
Figure 2.8. Input to Output Waveform for Single Channel Openldi/Fpd-LINK/LVDS, Rx Gear 14
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Figure 2.9. Input to Output Waveform for Dual Channel Openldi/Fpd-LINK/LVDS, Rx Gear 7
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Figure 2.10. Input to Output Waveform for Dual Channel Openldi/Fpd-LINK/LVDS, Rx Gear 14
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Figure 2.11. Output Pixel Data RGB Arrangement
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Figure 2.12. Output Pixel Data Arrangement for Single Channel Openldi/Fpd-LINK/LVDS
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Figure 2.13. Output Pixel Data Arrangement for Dual Channel Openldi/Fpd-LINK/LVDS
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Table 2.2. Output Pixel Data Summary
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Clock, Reset and Initialization
17
Reset and Initialization
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Clock Domains and Clock Domain Crossing
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Figure 2.14. Clock Domain Crossing Block Diagram
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Table 2.3. Clock Domain Crossing
17
Design and Module Description
18
FPD-Link Rx Wrapper Module
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Figure 2.15. FPD-Link Rx Wrapper Block Diagram
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FPD-Link Rx Module
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Figure 2.16. FPD-Link Rx Block Diagram
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Table 2.4. FPD-Link Rx Pin List Summary
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Table 2.5. FPD-Link Rx Parameter List
21
LVDS71 DDR Group Module
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Figure 2.17. LVDS71 DDR Group Block Diagram
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GDDR SYNC Module
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Figure 2.18. GDDR_SYNC Block Diagram
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Table 2.6. LVDS71 DDR Group Module Pin List
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Table 2.7. LVDS71 DDR Group Parameter List
23
BW ALIGN Module
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Clkdiv
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Eclksync
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Figure 2.19. BW_ALIGN Block Diagram
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Figure 2.20. CLKDIV Block Diagram
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Figure 2.21. ECLKSYNC Block Diagram
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Gpll
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LVDS71 Pixel Map Module
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Figure 2.22. GPLL Block Diagram
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Figure 2.23. LVDS71 Pixel Map Block Diagram
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Test Mode Module
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Table 2.8. LVDS71 Pixel Map Pin List Summary
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Table 2.9. LVDS71 Pixel Map Parameter List
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Figure 2.24. Test Mode Block Diagram
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Table 2.10. Test Mode Pin List Summary
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Table 2.11. Test Mode Parameter List
27
Synchronizer Module
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Figure 2.25. Synchronizer Block Diagram
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Figure 2.26. Synchronizer Timing Diagram
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Table 2.12. Synchronizer Pin List Summary
28
Table 2.13. Synchronizer Parameter List
28
3 Compiler Directives and Parameter Settings
29
Parameters Settings
29
Table 3.1. Openldi/Fpd-LINK/LVDS Receiver Interface IP Non-Packaged Parameter Settings
29
Table 3.2. Openldi/Fpd-LINK/LVDS Receiver Interface IP Parameter Settings
29
Compiler Directives
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Table 3.3. Openldi/Fpd-LINK/LVDS Receiver Interface IP Non-Packaged Compiler Directives
30
4 Debug Features
31
Test Mode
31
5 IP Generation and Evaluation
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Licensing the IP
32
Getting Started
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Figure 5.1. Clarity Designer Window
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Generating IP in Clarity Designer
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Figure 5.2. Starting Clarity Designer from Diamond Design Environment
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Figure 5.3. Configuring Openldi/Fpd-LINK/LVDS Receiver Interface IP in Clarity Designer
34
Generated IP Directory Structure and Files
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Figure 5.4. Configuration Tab in IP Interface
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Figure 5.5. Openldi/Fpd-LINK/LVDS Receiver Interface IP Directory Structure
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Table 5.1. Files Generated in Clarity Designer
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Running Functional Simulation
37
Table 5.2. Testbench Compiler Directives
37
Simulation Strategies
38
Simulation Environment
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Figure 5.6. Simulation Environment Block Diagram
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Figure 5.7. Two Rx Channels Configuration
38
Instantiating the IP
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Synthesizing and Implementing the IP
39
Figure 5.8. One Rx Channel Configuration
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Hardware Evaluation
40
Enabling Hardware Evaluation in Diamond
40
Updating/Regenerating the IP
40
Regenerating an IP in Clarity Designer
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Figure 5.9. IP Regeneration in Clarity Designer
40
References
41
Technical Support Assistance
41
Appendix A. Resource Utilization
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Table A.1. Resource Utilization
42
Appendix B. What Is Not Supported
43
Revision History
44
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