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KX-TVM200E / KX-TVM200NE
SH-CPU interface terminal (interrupt terminal)
N_IVDC_INT
N_VB_INT
N_CDHDL_INT
N_WE
External device control terminal (general-purpose port)
GPIO6 - GPIO1
External device control terminal (external chip select)
N_GCS1
N_LAN_CS
N_USB_CS
External device control terminal (HDD interface)
N_IDCS0
N_IDCS1
External device control terminal (DSP)
HBIL
HCNTL1 - HCNTL0
N_DSP_DS12 - N_DSP_DS1
DSP_RW
N_DSP_GATE
DSP_HRDY
N_DSP_HINT12 -
N_DSP_HINT1
External device control terminal (DPT (ECO) )
N_ECO_CS12 - N_ECO_CS1
N_ECO_RE
N_ECO_WE
N_ECO_GATE
N_ECO_WAIT
SRAM interface terminal
N_MCS2 - N_MCS1
N_MWE
N_MOE
MA18 - MA0
MD15 - MD0
McBSP0 timing control terminal
M02M
M0FS12 - M0FS1
McBSP1 timing control terminal
M18M
M1FS12 - M1FS1
LHWSEL
VM-Link interface terminal
SHW_CLK
SHW_FH
SHW_UHW1
SHW_DHW1
McBSP0 data (VM-Link bridge)
LDHW_D
LUHW_D
McBSP1 data
M1DX
M1DR
HDLC outside connection terminal
DPT_CLK
DPT_SYNC
I_DPTHW
O_DPTHW
Cch interrupt
OEP0
OSX
Mode terminal and user test terminal
MODE1 - MODE0
input
"L"Act
Interrupt signal (iVDC)
input
"L"Act
Interrupt signal (VB)
input
"L"Act
Interrupt signal (DSP)
input
"L"Act
Interrupt signal (Cch, HDLC)
inout
-
General-purpose I/O port
output
"L"Act
General-purpose chip select (area where wait number setting is
possible)
output
"L"Act
External chip select (LAN)
output
"L"Act
External chip select (USB)
input
"L"Act
IDE0 chip select
input
"L"Act
IDE1 chip select
output
-
Byte select signal
output
-
Register select signal
output
"L"Act
DSP chip select signal (12 devices)
output
-
Chip select signal (Area 5 high-order byte)
output
"L"Act
Chip select signal (Area 6 low-order byte)
input
"H"Act
"Read strobe"
input
"L"Act
Write strobe
output
"L"Act
ECO chip select signal (12 devices)
output
"L"Act
ECO read enable
output
"L"Act
ECO write enable
output
"L"Act
ECO data bus enable signal
input
"L"Act
ECO wait signal
output
"L"Act
SRAM chip select signal
output
"L"Act
SRAM write enable signal
output
"L"Act
SRAM output (read) enable signal
output
-
SRAM address bus
In/out
-
SRAM data bus
output
-
2.048MHz, McBSP0 transfer clock
output
-
McBSP0 frame signal
output
-
8.192MHz, McBSP1 transfer clock
output
-
McBSP1 frame signal
output
-
HW select signal
inout
posedge VM-Link timing clock
inout
-
VM-Link frame head pulse
output
-
VM-Link upstream data
input
-
VM-Link downstream data
input
-
Voice data output to DSP
output
-
Voice data input from DSP
output
-
Output of compressed voice data to DSP
input
-
Input of compressed voice data from DSP
input
posedge DPT transfer clock
input
-
DPT frame pulse
input
-
HDLC input data
output
-
HDLC output data
input
Fall
Cch frame signal. Detects the falling edge.
input
"H"Act
Highway on which Cch data is carried.
input
-
Mode select signal. The state of this terminal can be read from the CPU
through the iVDC register.
38
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