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EN 58
8.
TPN10.1E LA
8.6
Diagram
10-5-14 T2/S2
Block diagram
TSSYNC
TSVALID
CVDD12
DVDD33
TSDATA0
TSDATA1
CVDD12
TSDATA2
Pinning information
I
F
/
L
I
F
I
F
/
L
I
F
F
r
o
m
T
u
n
F
r
o
m
T
u
n
R
F
‐
A
G
R
F
‐
A
G
T
T
o
o
T
T
u
u
n
n
‐
I
I
F
F
‐
A
A
G
G
T
T
o
o
T
T
u
u
n
n
2
W
S
2
W
S
T
o
T
u
n
T
o
T
u
n
2013-Oct-18
IC Data Sheets
Tuner/Demodulator, B14, NT78820TL (IC U203)
GPA0
1
TSERR
2
3
4
TSCLK
5
VSS
6
7
GPB0
8
GPB1
9
GPB2
10
11
12
13
14
VSS
15
16
ADC
e
r
e
r
C
C
RF‐ AGC
e
e
r
r
C
C
IF‐ AGC
e
e
r
r
e
r
e
r
Clock
Gen.
2
7
M
H
z
2
7
M
H
z
Figure 8-12 Internal block diagram and pin configuration
NT78820TL
DVB‐ C
Demodulator
DVB T
Demodulator
DVB T2
Demodulator
PLL
PWR
3
.
3
V
1
1
.
.
2
2
5
5
V
V
3
.
3
V
back to
div. table
48
AVSS
47
XTALI
46
XTALO
45
AVDD33
44
AVDD12
43
VSS
42
GPA5
41
CVDD12
40
GPB7
39
GPB6
38
GPA3/UARTTX
37
RESETN
36
CVDD12
35
VSS
34
GPA2
33
GPA1
T
S
O
u
t
T
S
O
u
t
TSO
T
o
H
o
s
t
T
o
H
o
s
t
2
2
W
W
S
S
2WS
T
o
H
o
s
t
T
o
H
o
s
t
GPIO
G
G
P
P
I
I
O
O
D
e
b
u
g
D
e
b
u
g
Debug
T
o
P
C
T
o
P
C
19530_310_130724.eps
130724
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