MSI PM8M2-V Series Manual page 45

MS-7071 M-ATX Mainboard
than the original DRAMs.
SDRAM CAS Latency
This controls the CAS latency, which determines the timing delay (in clock
cycles) before SDRAM starts a read command after receiving it. Settings:
[1.5], [2.0], [2.5], [3.0]. [1.5] increases the system performance the most
while [3.0] provides the most stable performance.
Bank Interleaving
This field selects 2-bank or 4-bank interleave for the installed SDRAM.
Disable the function if 16MB SDRAM is installed. Settings: [Auto], [Disabled].
Precharge to Active (Trp)
This setting controls the number of cycles for Row Address Strobe (RAS)
to be allowed to precharge. If insufficient time is allowed for the RAS to
accumulate its charge before DRAM refresh, refresh may be incomplete
and DRAM may fail to retain data. This item applies only when synchronous
DRAM is installed in the system. Setting options: [2T] to [5T].
Active toPrecharge (Tras)
This setting determines the time RAS takes to read from and write to a
memory cell. Setting options: [6T] to [9T].
Active to CMD (Trcd)
When DRAM is refreshed, both rows and columns are addressed
separately. This setup item allows you to determine the timing of the
transition from RAS (row address strobe) to CAS (column address strobe).
The less the clock cycles, the faster the DRAM performance. Setting options:
[2T] to [5T].
REF to ACT/REF to REF (Trfc)
This setting determines the time RFC takes to read from and write to a
memory cell. Setting options: [12T], [13T], [14T], [15T].
Act (0) to Act (1) (TRRD)
When the DRAM Timing is set to [Manual], the field is adjustable. Speci-
fies the active-to-active delay of different banks. Setting options: [2T], [3T].
AGP & P2P Bridge Control
Preess <Enter> and the following sub-menu appears:
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