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Broadcom BCM7405 General Information Manual

Preliminary hardware data module
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PRELIMINARY HARDWARE DATA MODULE
BCM7405
General Information
7405-1HDM00-R
5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203
06/29/07
2/24/2008 9T6WP

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  • Page 1 PRELIMINARY HARDWARE DATA MODULE BCM7405 General Information 7405-1HDM00-R 5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 06/29/07 2/24/2008 9T6WP...
  • Page 2 , and the Connecting everything logo are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners.

  • Page 3: Table Of Contents

    Preliminary Hardware Data Module BCM7405 06/29/07 ABLE OF ONTENTS Document Overview..........................1-1 Overview .............................. 1-2 Functional Description ..........................1-3 Top-Level Overview ..........................1-4 Features............................1-5 Video Data Flow........................... 1-8 Overview ............................1-8 Compressed Video Input ......................1-8 Personal Video Recording ......................1-9 Digital Video Decompression......................
  • Page 4 Video and Graphics Display .......................1-36 Overview .............................1-36 Features ..........................1-36 Video Subsystem ........................1-36 Graphics Subsystem ......................1-38 Top Level Partitioning........................1-38 Video (Broadcom Video Network) Subblock Description ............1-39 AVC/MPEG-2/VC-1 Feeder ....................1-40 Video Feeder ........................1-40 Graphics Feeder ........................1-40 Video Scaler ........................1-41 Motion Adaptive De-interlacer .....................1-41 Film Grain Technology ......................1-42...
  • Page 5 Preliminary Hardware Data Module BCM7405 06/29/07 Capture Block ........................1-42 Digital Noise Reduction ......................1-43 DNR Operations ........................1-43 Digital Contour Removal ......................1-43 Graphics Subblock Description....................1-44 Scaler Overview ........................1-45 Feeder Architecture (Source and Destination) ..............1-46 Color Keying and Color Matrix Architecture ................ 1-47 Compositor Architecture .....................
  • Page 6 BCM7405 Preliminary Hardware Data Module 06/29/07 Buses ..........................1-62 DDR-SDRAM Memory Image Organization ................1-62 Digital Video Compression Standards .................1-62 Memory Accesses for Video Decompression ..............1-62 DDR Clock Generation........................1-62 MIPS4380 Processor Core.........................1-63 Overview .............................1-63 Architecture ..........................1-63 Micro-Architecture ........................1-64 EJTAG Debug Support........................1-64 Major Functional Blocks ......................1-65 Execution Unit ........................1-65...
  • Page 7 Preliminary Hardware Data Module BCM7405 06/29/07 Generic I/O Port Controller ......................1-77 SPI Master ..........................1-77 Programmable Queue ......................1-78 Wraparound Transfer Mode ....................1-78 Programmable Transfer Length ..................1-78 Programmable Transfer Delay .................... 1-78 Programmable Queue Pointer .................... 1-78 BSC Master ..........................
  • Page 8 BCM7405 Preliminary Hardware Data Module 06/29/07 JTAG ...........................1-92 EJTAG ..........................1-92 Power Features ..........................1-93 Power Modes for DDR DRAM Memory Controller ..............1-93 Power-Up Sequence ........................1-94 Hardware Signal Descriptions........................1-95 Pin Definition Notations ........................1-96 Pin Labels............................1-96 Pin Type ............................1-96 Power-On Strap Settings........................1-147 Timing and AC Characteristics ......................1-149 Data Transport Input Timing......................1-150...
  • Page 9 Preliminary Hardware Data Module BCM7405 06/29/07 3rd Overtone Crystal Oscillator....................1-169 External Components ....................... 1-170 SATA Crystal ..........................1-170 Electrical Characteristics ........................1-171 Absolute Maximum Ratings ......................1-172 Recommended Operating Conditions ....................1-172 Thermal Data ............................1-173 Thermal Data ........................... 1-174 Mechanical Characteristics ........................
  • Page 10 BCM7405 Preliminary Hardware Data Module 06/29/07 Bro adco m C orp or atio n Page x Document 7405-1HDM00-R 2/24/2008 9T6WP...
  • Page 11 Figure 1-1: Functional Block Diagram ......................1-7 Figure 1-2: Video Data Flow Diagram ......................1-8 Figure 1-3: Data Transport and Broadcom Security Processor Block Diagram ..........1-14 Figure 1-4: Data Transport I/O Connections Diagram................... 1-16 Figure 1-5: Advanced Video Decoding Module Block Diagram..............1-32 Figure 1-6: Audio Block Diagram........................
  • Page 12 BCM7405 Preliminary Hardware Data Module 06/29/07 Figure 1-33: Soft Modem Connections ......................1-91 Figure 1-34: Power-Up Sequence Waveforms Without On-chip Voltage Regulator........1-94 Figure 1-35: Data Transport Input Band Timing ..................1-150 Figure 1-36: MPOD Input Timing .........................1-151 Figure 1-37: RMX Serial Output Port Timing (Clock/Data/Sync Mode) ............1-152 Figure 1-38: MPOD Output Timing ......................1-153...
  • Page 13 Preliminary Hardware Data Module BCM7405 06/29/07 IST OF ABLES Table 1-1: Document Overview ........................1-2 Table 1-2: Video DAC Configuration ......................1-10 Table 1-3: Definition of Terms ........................1-15 Table 1-4: Decode and Display Formats ....................... 1-37 Table 1-5: Color and Alpha Selection......................1-48 Table 1-6: Digital Video Decoder Supported Modes ..................
  • Page 14 BCM7405 Preliminary Hardware Data Module 06/29/07 Table 1-34: DDR Interface Timing Parameters....................1-164 Table 1-35: Nominal DVO Output Propagation Delays................1-165 Table 1-36: Timing for ITU656 Output at vo_656 Pins ................1-166 Table 1-37: Timing for Alternate 656 Output at vi0_656 Pins ..............1-167 Table 1-38: Timing for Serial Teletext Output at rmx_data1 Pin ..............1-167...

  • Page 15: Document Overview

    Preliminary Hardware Data Module BCM7405 Document Overview 06/29/07 Ge ne ral In for mati o n OCUMENT VERVIEW Overview ............................Bro adco m Co rp or atio n Document 7405-1HDM00-R Page 1-1 2/24/2008 9T6WP...

  • Page 16: Table 1-1: Document Overview

    • Timing and AC Characteristics • Electrical Characteristics • Mechanical Drawing • Ordering Information 7405-2HDM0x Front-End Functions The BCM7405 does not contain Front-End Functions 7405-3HDM0x Data Transport, Audio, This document contains information on the following functionality: Video, and Graphics • Data Transport Processor •...

  • Page 17: Functional Description

    Ge ne ral In for mati o n UNCTIONAL ESCRIPTION Top-Level Overview ........................... Video Data Flow ..........................Data Transport Processor ........................ 1-11 Broadcom Security Processor ......................1-28 Advanced Video Decoder......................... 1-29 Advanced Audio Module ........................1-33 Video and Graphics Display ......................

  • Page 18: Top-Level Overview

    SCART1, SCART2, RGB and YPrPb component. The following output resolutions are supported: 480i, 480p, 576i, 576p, 720p, and 1080i. Six output DACs are available to be shared amongst the output functions. The BCM7405 also supports output over an HDMI interface and a Channel 3/4 RF Modulator. An ITU-R-656 output port with Teletext sideband is available if an interface to an additional external video encoder is desired.

  • Page 19: Features

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 The Macrovision enabled version of this device may only be sold or distributed to authorized Macrovision buyers. If you have a Macrovision enabled device, then the following applies: This device is protected by U.S. patent numbers 4,631,603,4,577,216 and 4,819,098 and other intellectual property rights.
  • Page 20 First MAC to connect to internal integrated 10/100 BASE-T PHY Second MAC to connect to MII interface The BCM7405 incorporates a complete MIPS 4380 Floating Point CPU microprocessor subsystem. including with bridging to memory and a local bus, where external peripherals can be attached. Integrated peripherals include the following: •...

  • Page 21: Figure 1-1: Functional Block Diagram

    Two IR receivers • IR blaster • UHF remote control receiver • BSC and SPI controllers Figure 1-1 on page 1-7 shows the BCM7405 functional block diagram. Configurable Dual Serial USB 2.0 PCI 2.3 and Flash USB 2.0 x2 64-bit DDR2 ATA-2...

  • Page 22: Video Data Flow

    IDEO VERVIEW At the top level, video signals flow through the video portion of the BCM7405 as compressed digital data or digitized baseband analog video. From the appropriate decoder (AVC/MPEG-2/VC-1 decompression or ITU-R-656 video decoding), the video data passes to the video processing stage where any scaling can be applied and the resulting video can be stored to memory for later display.

  • Page 23: Personal Video Recording

    ITU-R 656 I NPUT The BCM7405 supports an ITU-R 656 video input. The input has a dedicated VBI decoder to handle Teletext, NABTS, Close Caption, CGMS-A, Gemstar, and WSS. IDEO ROCESSING The display engine takes in uncompressed video from either the AVC/MPEG-2/VC-1 decoder or the digital ITU-R-656 input.

  • Page 24: Video Encoder

    The VEC outputs either an HD or SD stream on the first television output, and a scaled down version of an HD image on the second television output. The BCM7405 provides a single user experience that allows for simultaneous outputs of the same content for high definition and standard definition televisions.

  • Page 25: Data Transport Processor

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 RANSPORT ROCESSOR VERVIEW The data transport processor is an MPEG-2/DIRECTV transport stream message/PES parser and demultiplexer. It can simultaneously process 255 PID filters via 255 PID channels in up to six independent external transport stream inputs and five internal playback channels, with decryption for all 255 PID channels.
  • Page 26 Support DLNA timestamp format in record path • Support DLNA timestamp format in playback path • Includes Broadcom Security Processor with OTP for key generation. • Security features: Supports Passage as defined by Sony Supports Multi-Stream CableCard as defined by OpenCable Advanced Multi-Stream POD (MPOD) Interface...

  • Page 27: Functional Overview

    The RAVE supports up to a total of 32 SCDs (configured 0-8 per record channel). The data transport also provides four PCR recovery blocks and two serial STC broadcast block for transmitting the STC to the decoders. The Broadcom data transport processor, shown in Figure 1-3, is an MPEG-2/DIRECTV transport stream message/PES parser and demultiplexer.

  • Page 28: Figure 1-3: Data Transport And Broadcom Security Processor Block Diagram

    CSS, DTCP + Key table Timebase XMEM interface pulses Mem-to-Mem (not in Transport) I/F-0 Figure 1-3: Data Transport and Broadcom Security Processor Block Diagram Bro adco m C orp or atio n Page 1-14 Data Transport Processor Document 7405-1HDM00-R 2/24/2008 9T6WP...

  • Page 29: Table 1-3: Definition Of Terms

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 Table 1-3: Definition of Terms Term Definition Input Band Refers to the six external transport stream inputs supported by this design (IB0-5). Parser Band Refers to the transport streams that are selected as inputs to the six front end parsers or five playback channels to five playback parsers.

  • Page 30: Data Transport I/O Connections

    For other available options, refer "Data Transport" in the BCM7405 Programmer's Register Reference Guide. The data transport module provides one external parallel transport stream input. Input band 4 can be used as either serial or as parallel format.

  • Page 31: Pid Parser

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 PID Parser The data transport module supports six independent front-end PID parsers and five playback PID parsers. A 255-entry PID table is used to compare with the PIDs of the selected transport streams. Each PID channel consists of a primary PID filter and an optional secondary PID filter.

  • Page 32: Pid/Packet Substitution And Generation Module

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 Timestamp format is programmable—32 bit straight binary or modulo 300 for the nine LSB, similar to the MPEG PCR. Timestamp format can be selected independent of the transport packet format. Playback pacing supports both timestamp formats.

  • Page 33: Multistream Cablecard Interface

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 PSUB0 High priority PSUB1 High priority PSUB2 High priority PSUB3 High priority PSUB4 High priority PSUB5 High priority PSUB0 Low priority PSUB1 Low priority PSUB2 Low priority 10 PSUB3 Low priority 11 PSUB4 Low priority 12 PSUB5 Low priority There is a hardware timer per module, allowing automatic repeat of the entire insertion for each module.

  • Page 34: Condition Access Descramblers (The Downstream Descramblers)

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 Condition Access Descramblers (The Downstream Descramblers) The data transport module provides a DVB, 1DES, 3DES, AES, and a Multi2 descrambler for Conditional Access for up to 128 PID channels which may include video, audio, and data streams.

  • Page 35: Pes Parser

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 PES Parser The PES parser delineates PES packets and sends them to the message buffers. Any number of the PID channels 0-127 can be enabled for PES processing. When a complete PES packet is received, a data available interrupt is generated by the message buffer manager.

  • Page 36: Memory Buffer Manager

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 Each enabled generic filter is applied to MPEG section bytes 0-3, excluding byte 2. Banks of 4-byte generic filters can be cascaded to make up groups of filters that are effectively up to 64 bytes wide.
  • Page 37 Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 transport field tables which can then be used during playback to perform trick modes. RASP, as defined by NDS, can be supported using TPIT. Up to five record channels can be configured for the TPIT function.
  • Page 38 BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 The packet sync signal is used to determine the start of a transport packet, regardless of the current state of the transport parser. The PID must match the host CPU programmed packet ID.

  • Page 39: Audio/Video Interface

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 There are three counters in the transport field parser: • The packet counter: The packet counter counts all packets that are recorded. The packet count at the time an index table entry is made is part of the entry.

  • Page 40: Playback Sync Extractor

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 The playback module also includes a pacing function which can optionally pace the playback data using the local data transport timestamps (when the playback data was recorded with timestamps). Playback Sync Extractor The playback sync extractor engine generates the sync signal for TS and PES streams which are played from a playback memory buffer by the playback module.

  • Page 41: Pcr Recovery Block

    Loop filter is first order IIR filter. All LPF arithmetic is saturating and phase saturation interrupt is generated if final output saturates. Timebase loop allows the load integrator value to rapidly change the output frequency, but Broadcom does not normally recommend this.

  • Page 42: Serial Stc Broadcast Module

    STB security components together, Broadcom Security System design is an integrated security system controlled by BSP with a small real-time OS kernel that runs on its own master processor. The Broadcom Security Processor (BSP) supports various security features in an integrated STB SoC system such as: •...

  • Page 43: Advanced Video Decoder

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 • BSP can perform external memory data validation. For example, BSP can verify the signature of the codes stored in, for example, the off-chip program memory before the host CPU is authorized to execute these codes.

  • Page 44: Mpeg-4 Part2

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 AVC/H.264 • High profile, all levels up to and including 4.1 • Up to 40 Mb/sec. code stream bit rate • Adaptive block size, quantization matrixes The Advanced Video Decoder module decodes any bitstream coded with any combination of tools allowed under the Main Profile as defined in the ISO standard 14496-10, (MPEG-4 Part 10).

  • Page 45: Xvid

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 XVID XVID support with the exception of: • global motion compensation • 1/4-pel motion compensation MPEG-1/H.261/H.263 EATURES • Error concealment • SDRAM memory interface for code in and video out • Five SDRAM clients, three linear, two pixel •...

  • Page 46: Avd Block Diagram And Data Flow Description

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 AVD B LOCK IAGRAM AND ESCRIPTION Figure 1-5 shows a block diagram of the Advanced Video Decoder module. GISB GISB Bridge Outer Inner Loop Loop RISC RISC Symbol Interpreter Spatial Prediction Entropy...

  • Page 47: Advanced Audio Module

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 DVANCED UDIO ODULE The audio module consists of two main modules: DSP subsystem and Audio I/O (AIO). The main modules of the DSP subsystem consist of the DSP, data and instruction memories. The main functions of DSP subsystem include parsing audio and timing data from data transport, decompressing compressed data, time stamp management, and processing PCM data.

  • Page 48: Features

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 EATURES • The DSP System decodes any of: AAC-LC (ISO/IEC 13818-7) Input can be up to 5.1 channels with one coupling channel (dependent or independent) and up to 288-kbps per-channel. Output is downmixed to two channels. Supported sampling rates are 16 kHz, 32 kHz, 44.1 kHz, and 48 kHz.

  • Page 49: Overview Of Audio Module

    UDIO ODULE The BCM7405 audio core consists of DSP subsystem (RPTD) and audio input/output module (AIO). The RPTD is a DSP system block for decompression of MPEG, Dolby Digital, MPEG-2 AAC, MPEG-4 AAC, and Dolby Digital Plus audio services. The DSP system also supports a second digital audio path that allows simultaneous output of a digital audio service in compressed form on SPDIF.

  • Page 50: Video And Graphics Display

    The architecture goal of this new, modular approach is to allow various chip-sets to share the same basic component building blocks to achieve the customers design requirements. The BCM7405 employs enough of these building blocks to realize a dual video output with independent graphics on each output. Supported video decode and display format combinations can...

  • Page 51: Table 1-4: Decode And Display Formats

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 • Video scalers 2D scalers using an flexible FIR algorithm • Motion Adaptive Deinterlacing Adaptive de-interlacing for 480i or 576i input formats to 480p, 576p, 720p, and 1080i resolutions 3:2/2:2 pull-down detection and adaptive 3:2 pulldown progressive frame filtering •...

  • Page 52: Graphics Subsystem

    • BLT functions • ROP operations EVEL ARTITIONING The graphics and video engine of the BCM7405 is comprised of two major sections—the Memory-to-Memory Compositor and the BVN. Figure 1-7 illustrates these subblocks in the BCM7405. 2D BLT Engine 32-bit Internal Register Bus...

  • Page 53: Figure 1-8: Video Display Engine Block Diagram

    ETWORK UBBLOCK ESCRIPTION The BVN is a modular architecture that has been developed for the BCM7405. It is designed to allow the maximum flexibility to the end user in terms of allocating the available resources of the chip. Figure 1-8 illustrates the basic design of the BVN structure.

  • Page 54: Avc/Mpeg-2/Vc-1 Feeder

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 AVC/MPEG-2/VC-1 Feeder The AVC/MPEG-2/VC-1 feeder supports a number of frame buffer formats. In addition, a number of frame buffer formats commonly used by software codecs are included and registered in Microsoft as Four-Character Code (FOURCC). The scope is limited to 4:2:0 and 4:2:2 formats only, and other formats are not supported (such as 4:4:4).

  • Page 55: Video Scaler

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 W_RGB_1_565 • 16-bit formats RGB_565 WRGB_1555 RGBW_5551 ARGB_4444 RGBA_4444 AP_88 • 8-bit format • Other formats A horizontal scaler is either inside the graphics feeder or just downstream from it. This scaler can only handle horizontal upscaling, and has an 8-tap filter for this up-scaling function.

  • Page 56: Film Grain Technology

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 • Reverse 2:2 pull-down for improved quality from film based sources. • Optional CPU control over 2:2 cadence detection and correction. • Automatic handling of mixed interlaced, 3:2 and 2:2 pull-down •...

  • Page 57: Digital Noise Reduction

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 IGITAL OISE EDUCTION DNR reduces MPEG coding artifacts including block noise and mosquito noise. DNR is a BVN ready-accept block and is expected to operate immediately after the MPEG feeder(s.) To be effective, DNR must operate before any scaling or deinterlacing.

  • Page 58: Graphics Subblock Description

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 RAPHICS UBBLOCK ESCRIPTION The Memory-to-Memory Compositor interacts directly with memory only. There is no real-time processing of graphics (apart from the graphics feeder in the video block). This allows the graphics system to be divorced from the video that reduces the real-time scheduling (RTS) requirements.

  • Page 59: Scaler Overview

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 Compositor Block Diagram Figure 1-10 shows the system architecture of the Memory-to-Memory Compositor architecture. As depicted, the Memory-to- Memory Compositor consists of a collection of smaller, independent blocks. Specifically, there would be two feeders to access DRAM, a scaler that would handle any scale size (as well as filtering operations), a compositor to allow blending, a ROP generator, and a capture block.

  • Page 60: Feeder Architecture (Source And Destination)

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 Start Address Stripe Width Horiz. Width Stride Vert. Height Overlap Figure 1-11: Stripe Example Feeder Architecture (Source and Destination) The feeder module is responsible for accessing memory to fetch or retrieve the preferred graphics or video data. It is also responsible for basic format conversion and addressing control along with endian sensing.

  • Page 61: Color Keying And Color Matrix Architecture

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 • CrY0CbY1_8888 • CbY1CrY0_8888 • CbY0CrY1_8888 • 8-bit format • Other formats Color Keying and Color Matrix Architecture Due to the mathematical complexity of the color matrix, this block can only handle one pixel per clock at the maximum rate.

  • Page 62: Compositor Architecture

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 Color Keying One common requirement in any compositor operation is to allow color keying of data. This allows a particular color (or range of colors) to become transparent. Figure 1-12 illustrates the placement of the color keying operation along with the color conversion.

  • Page 63: Rop Architecture

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 ROP Architecture The ROP is the final stage of the compositor function. This allows a logical combination of operators to be applied to the output data. The ROP is realized in hardware by using an 8 to 1 multiplexor. The control signals are tied to the various inputs while the data inputs are tied to a programmed register.

  • Page 64: Digital Video Decoder (Itu-R-656)

    IDEO NCODER The BCM7405 employs a analog video encoder (VEC) with Macrovision 7.1 support capable of processing one high definition video stream and one standard definition (that is scaled down content from the high definition video stream). Instead of replicating identical modules, the VEC is built out of distinct block elements to meet the preferred customer requirements.

  • Page 65: Table 1-8: Analog Video Encoder

    NTSC Macrovision AGC and Macrovision Proprietary 1716x525 Color Stripe Type 3 720x480i@60 Hz NTSC - M/J (Japan) ITU-R BT.470-6 1716x525 720 x 240p@60 Hz Gaming Mode (North America Broadcom Internal Spec 1716x525 Set-top box) 720x576i@50Hz SECAM ITU-470.6 1728x625 720x576i@50 Hz ITU-R BT.470-6 1728X625...

  • Page 66: Vbi Encoding

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 Figure 1-13 illustrates a single-channel implementation of the VEC. By replicating select modules, this architecture can be expanded to meet any targeted requirement. V ideo 2 Input Tim ing V ideo 1...

  • Page 67: Video Dacs

    Nevertheless, the BCM7405 has included the Safe mode of operation for the DVI outputs. Internally, the BCM7405 generates a 25.2-MHz or 25.174-MHz clock to generate the correct clock signal for either the 60 or 59.94-Hz environments. The video is output at this rate through the DVI port in 640 x 480p resolution.

  • Page 68: Supported Modes

    1280x768@60 Hz WXGA VESA dmt09 1664x798 1366x768@60 Hz TFT LCD Chi Mei Model V320B1-L01 1440x782 1366x768@60 Hz Sharp Monitor Broadcom Internal Specifications 1440x782 1366x768@60 Hz Sharp Monitor Inverted Sync Broadcom Internal Specifications 1440x782 1024x768@60 Hz Plasma TV Broadcom Internal Specifications 1126x800...

  • Page 69: Supported Pc Scan Rates

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 Supported PC Scan Rates Table 1-12 Table 1-13 illustrate the clock rates that the DVI core can generate as well as the PC format resolutions that it can support. Table 1-12: DVI PC Scan Clock Rates...

  • Page 70: Rf Modulator

    Encoder modulator Figure 1-14: RF Modulator Block Diagram EATURES The Broadcom RFM is highly programmable and supports a variety of features: • Digital Audio Processor Flexibility allows support for FM-audio-based television standards B/G, D/K, H, I, K1, M, and N.

  • Page 71: Typical Usage Modes

    Supported Television Standards The intended purpose of the RFM on the BCM7405 chip is to allow the viewing of an analog RF modulated television signal on a television by modulating that signal to NTSC Channel 3 (61.25 MHz) or NTSC Channel 4 (67.25 MHz).

  • Page 72: Audio Transmission Modes

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 Audio Transmission Modes The RFM supports both monaural and stereo audio operation. More specifically, the RFM supports the following audio transmission capabilities: • MONO mode: Monaural transmission. • STEREO mode: BTSC or NICAM stereo encoding and transmission.

  • Page 73: Memory Controller

    Note that the BCM7405 has two set’s of Address/Control pins to mitigate interface timing issues at 400 MHz. The second set of Address/Control logic is simply muxed to Memory Controller Core-2 in Modes 4 and 5. For the BCM7405, it is also assumed that both the memory controller core gets the same clock.

  • Page 74: Figure 1-15: Memory Controller Partition

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 64-BIT DDR2 IOB UF Register Mem ory Controller Top Stage Integration Mem ory Controller Core – 1 Mem ory Controller Core - 2 Register Stage Figure 1-15: Memory Controller Partition Bro adco m C orp or atio n...

  • Page 75: Dram Physical Layer Controller

    32 MB is connected to 16-bit interface. The 128+64 MB (192 MB) device configuration can also be supported by the BCM7405 when 128 MB is hooked up to the 32-bit interface and 64 MB is connected to the 16-bit interface.

  • Page 76: Dram Transaction Layer Controller

    DRAM clock cycles while the DRAM is not being used by fixed-priority clients. Buses The BCM7405 memory controller is connected to the various modules within the device using system buses. The main bus has a 256 bit-wide data-path. DDR-SDRAM Memory Image Organization The advanced video decoder (AVC/MPEG/VC-1) cooperates with the DRAM controller optimizes the performance of the DRAM controller when decoding the more complex advanced formats.

  • Page 77: Mips4380 Processor Core

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 MIPS4380 P ROCESSOR VERVIEW This section highlights the features of the MIPS CPU architecture. All the application specifics, such as the cache configurations are also included. RCHITECTURE • Full MIPS32 architecture compliant...

  • Page 78: Micro-Architecture

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 ICRO RCHITECTURE • Standard MIPS32 six-stage pipeline • Multiply-divide unit (MDU) Latency of three and four cycles, respectively, for 32x32-multiply and multiply-accumulative operations Max issue rate of one 32x32 multiply and multiply accumulate operations every clock...

  • Page 79: Major Functional Blocks

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 AJOR UNCTIONAL LOCKS Figure 1-16 depicts a block diagram of the CPU. An overview of these functional blocks is presented in this section. JTLB CP 1 CP 1 JTLB eDSP MIPS16e MIPS16e...

  • Page 80: Multiply Divide Unit

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 • Pipeline control unit to orchestrate all the units and to resolve inter-instruction dependency. This includes the register- file bypass multiplexers used to resolve data dependency between consecutively executed instructions. • MDU and eDSP instructions described below •...

  • Page 81: Edsp Extended Instructions

    XTENDED NSTRUCTIONS The eDSP extended instructions are Broadcom-specific instructions and are implemented as part of the MDU. The extended instructions are defined in the MIPS32 SPECIAL2 space for an application to perform 16-bit DSP computation such as multiply-add, multiply-subtract, saturate, shift-left, and their combinations. In particular, the eDSP instructions in the CPU can execute SIMD (dual-MAC) instructions and perform direct load and store operations from Hi/Lo accumulators.

  • Page 82: System Control Coprocessor (Cp0)

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 Because the TLB is shared by the instructions and data translations, it is also called the Joint TLB, or JTLB. There are 4- entry I-TLB and D-TLB served as caches of the JTLB for fast lookup of instruction and data address translation.

  • Page 83: Level-Two Cache

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 EVEL ACHE The CPU has an on-core Level-Two (L2) cache, which is physically indexed and tagged. The L2 cache is shared by all the TPs and can be viewed as the extension of all the L1 caches. When a miss of one of the L1 caches hits the L2 cache, the L2 line and the line being replaced from the L1 cache are swapped between the L1 and L2 caches.

  • Page 84: Debugging Support Unit

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 EBUGGING UPPORT The CPU processor provides standard EJTAG support that is in compliant with the MIPS EJTAG 2.0. Basic support includes a debug mode, run control, single stepping, and software breakpoint instruction (SDBBP). These features allow for the basic software debug of user and kernel code.

  • Page 85: Peripherals

    ERIPHERALS VERVIEW The BCM7405 provides common peripherals used for set-top box control. In addition, there is an external bus interface to support connection of external devices like SRAM and flash memories. The BCM7405 also has several advanced connectivity features including Ethernet, Serial ATA, and USB.

  • Page 86: Ir Blaster Controller

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 encoding. A programmable noise filter, located before the decoders, can be configured to filter out narrow spikes and glitches. IR B LASTER ONTROLLER The IR blaster controller takes data sent from the microcontroller and loads it into the blaster's control logic. The data is converted into a coded format compatible with the user's VCR or handheld remote display.
  • Page 87 Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 16-bit count values within the modulating register file are used to control the modulating pulse widths for both Flash IR and Carrier IR schemes. The actual time duration of these waveforms is based on the value in the BLAST_PRIMPRE register as well as the value in the modClk field of the BLAST_INDXPRE register, and is given by (1 tick) = ([reg_clk_period] * [primClk + 1] * [modClk + 1]) where reg_clk_period = 1/27 MHz = 37 ns.

  • Page 88: Uhf Receiver

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 UHF R ECEIVER The UHF receiver consists of an analog front end (AFE) and a digital front end (DFE). Data packet decoding is done in IR Receiver Controller. The AFE converts RF FSK-modulated signals in a band from 350 to 450 MHz down to an IF of 10.7 MHz. In terms of sensitivity, it can operate from -102 dBm to -30 dBm.

  • Page 89: Uart

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 Digitally Sampled IF Signal(from AFE) Anti-Aliasing Filter Filter To Data Decoder Adaptive Frequency Slicer Discriminator Anti-Aliasing Filter Filter Carrier offset 10 .7MHz Figure 1-21: Digital Front End of UHF Receiver The data decoder extracts the data packet from the binary FSK datastream generated from DFE. Data decoding is performed by the Consumer IR (CIR) decoder in the IR Receiver Controller.

  • Page 90: Functional Description

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 Receive Receiver Data FIFO Control and Status Registers Baud Baud Rate Rate Register Generator Transmit Data Transmitter FIFO Figure 1-22: UART Functional Block Diagram Functional Description Asynchronous Communications Encoding The UART handles standard asynchronous NRZ encoded format with seven or eight bits/characters, one stop bit/character, and even, odd, or no parity.

  • Page 91: Generic I/O Port Controller

    = 16 x (baud_rate + 1) This formula allows a bit rate of 1/16 to 1/262144 of the input frequency. For the BCM7405, the input frequency is 27 MHz. Receiver The receiver functions as a serial-to-parallel converter. The rxd pin is sampled at 16 times the data rate using a clock from the Baud Rate Generator.

  • Page 92: Programmable Queue

    Segmenting the queue allows the host to support multitasking operations. BSC M ASTER The BCM7405 includes four BSC master ports. Master clock rate can be selected from the following possibilities based on internal clock dividers from the 27-MHz clock: •...

  • Page 93: Bsc Master Interface Operation

    BCM7405 Functional Description 06/29/07 Arbitration process (required with multiple BSC masters). It is assumed that BCM7405 is the only device equipped with BSC master capability. BSC Master Interface Operation This BSC master interface can be configured to perform four different combinations of transmitting (WRITE) and receiving (READ) data from a slave device by setting appropriate data transfer format (DTF) of the control register: •...

  • Page 94: Pwms

    MART NTERFACES The BCM7405 has two identical and independent Smart Card interfaces. Each interface has an ISO 7816 UART with a 16- character deep receive FIFO, automatic convention processing, variable baud rate, automatic error management at the character level, and automatic insertion of extra guard time. Each interface also has pins for controlling the card VCC and RST, and a pin for card presence.

  • Page 95: Features

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 Features • ISO 7816 UART with 264-byte receive and transmit buffers • Interrupt Controller with 14 sources allowing fully interrupt controlled operation and monitoring using minimal CPU overhead • Asynchronous T=0 and T=1 modes fully supported •...

  • Page 96: M-Card Cpu Interface

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 CPU I NTERFACE Introduction MCIF is the CPU interface controller for the Multi-Stream CableCARD and is illustrated in Figure 1-26. The physical interface is a modified SPI (Serial Peripheral Interface). The data changes on the falling edge of the clock (SCLK, 6.75 MHz) and clocked in on the rising edge.

  • Page 97: Input And Output Processes

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 RBUS CPU/PCI MCIF HOST M-CARD signals M-CARD Figure 1-27: MCIF Interfaces Input and Output Processes Output To M-CARD TX_BUF_PTR points to the start of the buffer where data is kept. It should contain the whole packet segment data up to a maximum size of 4096 bytes.

  • Page 98: Pci And External Bus Interface

    CSb is not asserted. Both EBI and PCI interfaces operate at a max clock frequency of 33 MHz. Software running on the internal MIPS processor can allow the BCM7405 to act as a PCI South bridge. This allows an easier migration path for external processors to access the peripheral devices (such as the USB controller).

  • Page 99: Figure 1-28: Ebi Synchronous Read Cycle Between Two Pci Cycles

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 PCI_CLK EBI_CSb EBI_TSb EBI_DSb EBI_RDb EBI_WEb[1:0] EBI_ADDR[25:24] EBI Address EBI_TSIZE[1:0] EBI Valid Tsize PCI_AD[15:0] PCI Data PCI Data Addr Data Addr (EBI_DATA[15:0]) PCI_AD[31:16] EBI Address PCI Data (EBI_ADDR[15:0]) Addr Addr Data PCI_CBE[3:0]...

  • Page 100: Figure 1-29: Ebi Asynchronous Read Cycle Between Two Pci Cycles

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 PCI_CLK EBI_CSb EBI_RWb EBI_DSb EBI_RDb EBI_WEb[1:0] EBI_ADDR[25:24] EBI Address EBI_TSIZE[1:0] EBI Valid Tsize PCI_AD[15:0] PCI Data PCI Data Addr Data Addr (EBI_DATA[15:0]) PCI_AD[31:16] EBI Address PCI Data (EBI_ADDR[15:0]) Addr Addr Data PCI_CBE[3:0]...

  • Page 101: Figure 1-30: Ebi Asynchronous Write Cycle Between Two Pci Cycles

    Preliminary Hardware Data Module BCM7405 Functional Description 06/29/07 PCI_CLK EBI_CSb EBI_RWb EBI_DSb EBI_WEb[1:0] EBI_RDb[1:0] EBI_ADDR[25:24] EBI Address EBI_TSIZE[1:0] EBI Valid Tsize PCI_AD[15:0] EBI Data PCI Data PCI Data (EBI_DATA[15:0]) Addr Addr PCI_AD[31:16] EBI Address PCI Data Addr Addr Data (EBI_ADDR[15:0])

  • Page 102: Figure 1-31: Ebi Synchronous Write Cycle Between Two Pci Cycles

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 PCI_CLK EBI_CSb EBI_TSb EBI_DSb EBI_WEb[1:0] EBI_RDb[1:0] EBI_ADDR[25:24] EBI Address EBI_TSIZE[1:0] EBI Valid Tsize PCI_AD[15:0] EBI Data PCI Data PCI Data (EBI_DATA[15:0]) Addr Addr PCI_AD[31:16] EBI Address PCI Data Addr Addr Data (EBI_ADDR[15:0])

  • Page 103: Advanced Connectivity Interface

    FIFO. Serial ATA Controller The BCM7405 integrates a dual serial ATA disk drive control module and dual physical layer interfaces on chip. The dual high-performance multiport SATA module contains two SATA 2.0 compliant controllers with integrated Physical layers and connects directly to a PCI Bus (32/64 bit, 33/66 MHz) on the host side.

  • Page 104: Usb

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 18 IN - MISC 22 OUT - MISC 81 IN - PCI 92 OUT- PCI I/O BUFFERS sata2_top PCI I/F CLOCK MUX PCI REGS HOST I/F HOST I/F BERT TPORT TPORT LINK...

  • Page 105: Soft Modem

    BCM7405. Software running on the internal MIPS32 processor can allow the BCM7405 to act as a South bridge. This allows an easier migration path for external processors to access the peripheral devices (such as the USB controller). The PCI bus operates at 33 MHz.

  • Page 106: Testability

    BCM7405 Preliminary Hardware Data Module Functional Description 06/29/07 ESTABILITY VERVIEW The BCM7405 uses a combination of production, functional and on-board tests. RODUCTION ESTING Scan Scan logic is inserted and ATPG vectors are created that exercise the scan chains. Built-In Self-Test Internal SRAM modules are examined by a Built-In Self-Test (BIST) sequence.

  • Page 107: Table 1-17: Power Estimate

    06/29/07 OWER EATURES The BCM7405 has been designed with some power saving features. To save power, the clock to sections of the chip can be turned off. Other possible power savings are currently being examined. Table 1-17 illustrates the power saving options based on just the clocking feature. Transport, memory controller, GPIO, remote controls, and CPU are assumed operational in low power mode.

  • Page 108: Figure 1-34: Power-Up Sequence Waveforms Without On-Chip Voltage Regulator

    EQUENCE The BCM7405 can accept any of the power rail sequence but all should be stable within 20 ms from any power rail raising past 50 mV. The RESETb signal should be held active for 75 ms after the last power rail has stabilized.

  • Page 109: Hardware Signal Descriptions

    Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Ge ne ral In for mati o n ARDWARE IGNAL ESCRIPTIONS Pin Definition Notations ........................1-96 Power-On Strap Settings........................ 1-147 Bro adco m Co rp or atio n Document 7405-1HDM00-R Page 1-95...

  • Page 110: Table 1-19: Pin Descriptions

    BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 EFINITION OTATIONS ABELS • A bar across the top of a pin name represents an active-low digital signal. • A b after the capital name of a signal represents an active-low digital signal.
  • Page 111 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) Video Connections Video DAC Interface – 18 4 - Video DAC VDAC0_0 –...
  • Page 112 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 3 - Digital Video VO_656_2 – AM33 ITU-R-656 Video Output. Output Shared with LED_LD_2 /...
  • Page 113 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 7 - Digital Video HDMI_CEC_T – – Consumer electronic control 7 - Digital Video HDMI_CEC –...
  • Page 114 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 9 - Analog Audio/ AUD0_RIGHT – – Right audio differential Digital Audio output (6mA 2.5V, 13.5...
  • Page 115 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 12 - Clocks DDR_EXT_CL Ext PU SSTL – DDR DRAM External Clock 14 - 64 Bit DDR2...
  • Page 116 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 14 - 64 Bit DDR2 DDR01_A10 Ext PU SSTL – Shared DDR DRAM...
  • Page 117 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 14 - 64 Bit DDR2 DDR23_A09 Ext PU SSTL – Shared DDR DRAM...
  • Page 118 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 14 - 64 Bit DDR2 DDR0_DQ04 Ext PU SSTL – DDR DRAM Data bus for...
  • Page 119 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 14 - 64 Bit DDR2 DDR1_DQ11 Ext PU SSTL – DDR DRAM Data bus for...
  • Page 120 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 14 - 64 Bit DDR2 DDR3_DQ02 Ext PU SSTL – DDR DRAM Data bus for...
  • Page 121 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 14 - 64 Bit DDR2 DDR0_DQS0b Ext PU SSTL – DDR DRAM Data Strobe...
  • Page 122 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 1 - PCI Bus/EBI PCI_AD01 Ext PU 3.3 – AM19 PCI Address / Data bus.
  • Page 123 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 1 - PCI Bus/EBI PCI_AD23 Ext PU 3.3 – AL25 PCI Address / Data bus.
  • Page 124 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 1 - PCI Bus/EBI PCI_INT_A1 Ext PU 3.3 – AP31 PCI interrupt[2:1] inputs...
  • Page 125 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 2 - Extended Bus EBI_RDb – AN17 Read control (OE) for Interface/Reset In/Out asynchronous memory.
  • Page 126 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 13 - Analog I/O UHF_IN_P – – UHF receiver positive differential input System Side Device – 3...
  • Page 127 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 15 - Ethernet/USB/ USB_MONCD – – CDR monitor SATA 11 - UHF/Video/HDMI/ USB_AVDD33 APWR –...
  • Page 128 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) Peripherals Serial ATA Interface (2 port) – 18 15 - Ethernet/USB/ SATA_RXDP1 –...
  • Page 129 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) Miscellaneous Signals – 125 2 - Extended Bus RESETb AP13 Hardware reset control...
  • Page 130 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 16 - GPIO GPIO_009 STI/O AB33 Generic I/O port. Shared with MII_TX_CLK / UART_CTS_1 / EXT_GFX_16 / Ext.
  • Page 131 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 16 - GPIO GPIO_020 STI/O Generic I/O port. Shared with PWM_0 / Ext. IRQb_13...
  • Page 132 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 16 - GPIO GPIO_033 STI/O Generic I/O port. Shared with POD2CHIP_MDI2 / PPKT_DATA2 /...
  • Page 133 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 16 - GPIO GPIO_045 STI/O Generic I/O port. Shared with CHIP2POD_MDO3 / RMXP_DATA3 /...
  • Page 134 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 16 - GPIO GPIO_054 STI/O AG31 Generic I/O port. Shared with PKT_ERROR3 / UART_RTS_2 / Ext.
  • Page 135 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 22 - GPIO GPIO_066 STI/O AH33 Generic I/O port. Shared with PKT_CLK3 /...
  • Page 136 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 22 - GPIO GPIO_081 STI/OD Ext PU 5 AK13 Generic I/O port. Shared with SC_IO_1 / NDS_SC_IO / Ext.
  • Page 137 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 22 - GPIO GPIO_095 STI/O Generic I/O port. Shared with LED_LD_0 / MII_MDC...
  • Page 138 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 22 - GPIO GPIO_109 STI/O Generic I/O port. Shared with CODEC_SDI / Ext.
  • Page 139 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 11 - UHF/Video/HDMI/ CLK54_XVDD APWR – – CLK54 XTAL Power Supply RFM/AUDIO/... 25_0 (2.5V +5% / -5%)
  • Page 140 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 12 - Clocks OBSRV_PLL – Observability for main PLL 12 - Clocks VCXO_OBSR –...
  • Page 141 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 17 - D3.3V VDDO – AH25 Digital Power Supply (3.3V I/O ±10%) 17 - D3.3V VDDO –...
  • Page 142 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 19 - D2.5V VDDP – AH15 Digital Power Supply (2.5V I/O ±10%) 19 - D2.5V VDDP –...
  • Page 143 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 20 - D1.2V VDDC – AC22 Digital Power Supply (1.2V core ±5%) 20 - D1.2V VDDC –...
  • Page 144 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 20 - D1.2V VDDC – AA24 Digital Power Supply (1.2V core ±5%) 20 - D1.2V VDDC –...
  • Page 145 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 20 - D1.2V VDDC – AE17 Digital Power Supply (1.2V core ±5%) 20 - D1.2V VDDC –...
  • Page 146 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 20 - D1.2V VDDC – AD13 Digital Power Supply (1.2V core ±5%) 20 - D1.2V VDDC –...
  • Page 147 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 18 - DDR2 1.8V DDRV – Digital Power Supply (DDR0) (1.8V I/O ±5%) 18 - DDR2 1.8V...
  • Page 148 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 18 - DDR2 1.8V DDRV – Digital Power Supply (DDR0) (1.8V I/O ±5%) 18 - DDR2 1.8V...
  • Page 149 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 21 - DGND/AGND DVSS – – Digital Ground 21 - DGND/AGND DVSS –...
  • Page 150 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 21 - DGND/AGND DVSS – – Digital Ground 21 - DGND/AGND DVSS –...
  • Page 151 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 21 - DGND/AGND DVSS – – Digital Ground 21 - DGND/AGND DVSS –...
  • Page 152 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 21 - DGND/AGND DVSS – – AJ12 Digital Ground 21 - DGND/AGND DVSS –...
  • Page 153 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 21 - DGND/AGND DVSS – – Digital Ground 21 - DGND/AGND DVSS –...
  • Page 154 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 21 - DGND/AGND VDAC_AVSS – – Analog Ground 21 - DGND/AGND VDAC_AVSS –...
  • Page 155 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) 21 - DGND/AGND EPHY_AVSS – – Analog Ground 21 - DGND/AGND USB_AVSS –...
  • Page 156 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) DEPOP – – – – Depopulated Balls DEPOP – – – – AP12...
  • Page 157 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) DEPOP – – – – AF14 Depopulated Balls DEPOP – – – –...
  • Page 158 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) DEPOP – – – – Depopulated Balls DEPOP – – – – Depopulated Balls DEPOP –...
  • Page 159 Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) DEPOP – – – – AE26 Depopulated Balls DEPOP – – – –...
  • Page 160 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-19: Pin Descriptions (Cont.) # of Orcad Schematic Tol. Drv. Label Res. Loc. Description Pins Block (mA) DEPOP – – – – Depopulated Balls DEPOP – – – – Depopulated Balls DEPOP –...

  • Page 161: Table 1-20: Power-On Strap Settings

    Preliminary Hardware Data Module BCM7405 Hardware Signal Descriptions 06/29/07 OWER TRAP ETTINGS Table 1-20: Power-On Strap Settings Strap Bit Description Default Comments strap_reset_ext_ Reset Extension Mode. VO_656_4 – mode 0: No delay 1: 200 ms (EBI_CS# delayed by 1.6 strap_reset_outb_...
  • Page 162 BCM7405 Preliminary Hardware Data Module Hardware Signal Descriptions 06/29/07 Table 1-20: Power-On Strap Settings Strap Bit Description Default Comments strap_ebi_invert_addr 0: Do not invert EBI address EBI_RDb 1: Invert upper bits of EBI address strap_boot_rom_type 0: Boot ROM is NOR Flash...

  • Page 163: Timing And Ac Characteristics

    Preliminary Hardware Data Module BCM7405 Timing and AC Characteristics 06/29/07 Ge ne ral In for mati o n AC C IMING AND HARACTERISTICS Data Transport Input Timing......................1-150 MPOD Input Timing ........................1-151 Data Transport Output Timing ......................1-152 MPOD Output Timing ........................

  • Page 164: Figure 1-35: Data Transport Input Band Timing

    BCM7405 Preliminary Hardware Data Module Timing and AC Characteristics 06/29/07 RANSPORT NPUT IMING IB_CLK (rising edge) IB_CLK (falling edge) IB_DATA, IB_SYNC Figure 1-35: Data Transport Input Band Timing Table 1-21: Data Transport Input Band Timing Parameters Description Symbol Min. Max.

  • Page 165: Figure 1-36: Mpod Input Timing

    Preliminary Hardware Data Module BCM7405 Timing and AC Characteristics 06/29/07 MPOD I NPUT IMING i_MPOD_CLK i_MPOD_SYNC, i_MPOD_DATA[1:0] Figure 1-36: MPOD Input Timing Table 1-22: MPOD Input Timing Parameters Description Symbol Min. Max. Units i_MPOD_CLK frequency – Trise – i_MPOD_CLK rise time Tfall –...

  • Page 166: Figure 1-37: Rmx Serial Output Port Timing (Clock/Data/Sync Mode)

    BCM7405 Preliminary Hardware Data Module Timing and AC Characteristics 06/29/07 RANSPORT UTPUT IMING RMX S ERIAL UTPUT IMING LOCK RMX_CLK (inverted) RMX_CLK (normal) RMX_DATA, RMX_SYNC Figure 1-37: RMX Serial Output Port Timing (Clock/Data/Sync Mode) Table 1-23: RMX Serial Output Port Timing (Clock/Data/Sync Mode) Parameters...

  • Page 167: Figure 1-38: Mpod Output Timing

    Preliminary Hardware Data Module BCM7405 Timing and AC Characteristics 06/29/07 MPOD O UTPUT IMING o_MPOD_CLK o_MPOD_SYNC, o_MPOD_DATA[1:0] Figure 1-38: MPOD Output Timing Table 1-24: MPOD Output Timing Parameters Description Symbol Min. Max. Units o_MPOD_CLK clock frequency – Trise – o_MPOD_CLK clock rise time Tfall –...

  • Page 168: I2S Audio/Compressed I2S Output Timing

    BCM7405 Preliminary Hardware Data Module Timing and AC Characteristics 06/29/07 UDIO OMPRESSED UTPUT IMING Figure 1-39: I S Audio/Compressed I S Output Timing Diagram Table 1-25: I S Audio/Compressed I S Output Timing Parameters Description Symbol Typical Units edge of sclk to changing lr clock clk_lr –4...

  • Page 169: Figure 1-40: Spdif Audio Output Timing Diagram

    Preliminary Hardware Data Module BCM7405 Timing and AC Characteristics 06/29/07 SPDIF A UDIO UTPUT IMING Figure 1-40: SPDIF Audio Output Timing Diagram Table 1-26: SPDIF Audio Output Timing Parameters Description Symbol Typical Units Unit Interval for Fs = 96 kHz UI_96 –...

  • Page 170: Figure 1-41: Dac Audio Output Timing Diagram

    BCM7405 Preliminary Hardware Data Module Timing and AC Characteristics 06/29/07 DAC A UDIO UTPUT IMING Figure 1-41: DAC Audio Output Timing Diagram Table 1-27: DAC Audio Output Timing Parameters Description Symbol Typical Units Pulse width – – Bro adco m C orp or atio n...

  • Page 171: Figure 1-42: 256Fs Audio Clock Output Timing Diagram

    Preliminary Hardware Data Module BCM7405 Timing and AC Characteristics 06/29/07 256F UDIO LOCK UTPUT IMING 256Fs_CLK Figure 1-42: 256Fs Audio Clock Output Timing Diagram Table 1-28: 256Fs Audio Clock Output Timing Parameters Description Symbol Typical Units 256Fs_CLK period for Fs = 96 kHz Tp_96kHz –...

  • Page 172: Figure 1-43: Pci Interface Timing Diagram

    BCM7405 Preliminary Hardware Data Module Timing and AC Characteristics 06/29/07 PCI I NTERFACE IMING high PCI_CLK PCI Outputs PCI Tri-state Outputs PCI Inputs Figure 1-43: PCI Interface Timing Diagram Table 1-29: PCI Interface Timing Parameters Description Symbol Units PCI CLK Cycle Time –...

  • Page 173: Figure 1-44: Async Read Timing Diagram

    Preliminary Hardware Data Module BCM7405 Timing and AC Characteristics 06/29/07 EBI T IMING SYNCHRONOUS RANSFER EBI_CLK EBI_ADDR[25:0] EBI_TSIZE[1:0] EBI_CSb[n] EBI_RDb, EBI_DSb EBI_DATA[15:0] Data Data Figure 1-44: Async Read Timing Diagram Table 1-30: Async Read Timing Parameters Description Symbol Min Units Delay time: EBI_CLK rising to EBI_ADDR[25:0] or EBI_TSIZE[1:0] valid 13.5...

  • Page 174: Figure 1-45: Async Write Timing Diagram

    BCM7405 Preliminary Hardware Data Module Timing and AC Characteristics 06/29/07 SYNCHRONOUS RITE RANSFER EBI_CLK EBI_ADDR[25:0] EBI_TSIZE[1:0] EBI_CSb[n] EBI_WEb, EBI_DSb EBI_DATA[15:0] Data Data Figure 1-45: Async Write Timing Diagram Table 1-31: Async Write Timing Parameters Description Symbol Min Units Delay time: EBI_CLK rising to EBI_DATA[15:0] valid Delay time: EBI_CLK rising to EBI_WEb[1:0] or EBI_DSb low or high 13.5...

  • Page 175: Figure 1-46: Synchronous Read Timing Diagram

    Preliminary Hardware Data Module BCM7405 Timing and AC Characteristics 06/29/07 YNCHRONOUS RANSFER EBI_CLK EBI_ADDR[25:0] EBI_TSIZE[1:0] EBI_TSb EBI_CSb[n] EBI_RWb EBI_DATA[15:0] Data Data EBI_TAb Figure 1-46: Synchronous Read Timing Diagram Table 1-32: Synchronous Read Timing Parameters Description Symbol Min Units Delay time: EBI_CLK rising to EBI_ADDR[23:0] valid Delay time: EBI_CLK rising to EBI_ADDR[25:24] or EBI_TSIZE[1:0] valid 13.5...

  • Page 176: Figure 1-47: Synchronous Write Timing Diagram

    BCM7405 Preliminary Hardware Data Module Timing and AC Characteristics 06/29/07 YNCHRONOUS RITE RANSFER EBI_CLK EBI_ADDR[25:0] EBI_TSIZE[1:0] EBI_TSb EBI_CSb[n] EBI_RWb EBI_DATA[15:0] Data Data EBI_TAb Figure 1-47: Synchronous Write Timing Diagram Table 1-33: Synchronous Write Timing Parameters Description Symbol Units Delay time: EBI_CLK rising to EBI_DATA[15:0] changing Note: •...

  • Page 177: Figure 1-48: Write Cycle Timing

    Preliminary Hardware Data Module BCM7405 Timing and AC Characteristics 06/29/07 DDR I NTERFACE IMING CLK / CLKb COMMAND ADRS/BSx Tdqss Tdpwo Figure 1-48: Write Cycle Timing CLK / CLKb COMMAND ADRS/BSx Tdpwi Tdv_read Figure 1-49: Read Cycle Timing Bro adco m Co rp or atio n...

  • Page 178: Table 1-34: Ddr Interface Timing Parameters

    BCM7405 Preliminary Hardware Data Module Timing and AC Characteristics 06/29/07 Table 1-34: DDR Interface Timing Parameters S.No Parameter Notation Min (ns) Max (ns) Clk Period Clk high level width – Clk Low level width – RASb output setup time w.r.t clk –...

  • Page 179: Figure 1-50: Clock-To-Data Timing

    Preliminary Hardware Data Module BCM7405 Timing and AC Characteristics 06/29/07 HDMI clkp data/ctl Figure 1-50: Clock-to-Data Timing The configuration values used to adjust the skew settings are all in the HDMI_MISC_CONTROL registers. Refer to the BCM7038 Programmer’s Register Reference Guide for more details.

  • Page 180: Figure 1-51: Itu656 Output Timing Diagram

    BCM7405 Preliminary Hardware Data Module Timing and AC Characteristics 06/29/07 ITU656 O UTPUT IMING Figure 1-51: ITU656 Output Timing Diagram The clock signal is a 27-MHz square wave. The positive transition of the clock signal occurs midway between data transitions.

  • Page 181: Figure 1-52: Serial Teletext Port Output Timing Diagram

    Preliminary Hardware Data Module BCM7405 Timing and AC Characteristics 06/29/07 656 O 0_656 P IMING LTERNATE UTPUT AT VI Table 1-37: Timing for Alternate 656 Output at vi0_656 Pins Timing (td) Min Timing (td) Max vi0_656_0 17.786 ns 19.494 ns vi0_656_1 17.862 ns...

  • Page 182: Crystal Requirements

    BCM7405 Preliminary Hardware Data Module Crystal Requirements 06/29/07 Ge ne ral In for mati o n RYSTAL EQUIREMENTS Crystal Requirements ........................1-169 Bro adco m C orp or atio n Page 1-168 ITU656 Output Timing Document 7405-1HDM00-R 2/24/2008 9T6WP...

  • Page 183: Table 1-39: Electrical Specifications

    BCM7405 Crystal Requirements 06/29/07 RYSTAL EQUIREMENTS The following lists are the known crystal and clock input requirements and constraints for the BCM7405 device. VERTONE RYSTAL SCILLATOR The 3 overtone crystal oscillator uses a 54-MHz crystal operating at the third overtone to generate the internal clock required for the BCM7405.

  • Page 184: Figure 1-53: Example: Vendor (Txc) Part Number For 3Ot Crystal: 7Ea0000023

    BCM7405 Preliminary Hardware Data Module Crystal Requirements 06/29/07 XTERNAL OMPONENTS An external filter is required for the differential oscillator to operate in its 3 Overtone mode. The required board components for proper 3 overtone crystal oscillator operation: Inductors - 10% tolerance; Capacitors - 5% tolerance;...

  • Page 185: Electrical Characteristics

    Preliminary Hardware Data Module BCM7405 Electrical Characteristics 06/29/07 Ge ne ral In for mati o n LECTRICAL HARACTERISTICS Absolute Maximum Ratings......................1-172 Recommended Operating Conditions .................... 1-172 Bro adco m Co rp or atio n Document 7405-1HDM00-R Page 1-171 2/24/2008 9T6WP...

  • Page 186: Table 1-41: Absolute Maximum Ratings

    BCM7405 Preliminary Hardware Data Module Electrical Characteristics 06/29/07 BSOLUTE AXIMUM ATINGS Table 1-41: Absolute Maximum Ratings Parameter Symbol Unit Digital Core Supply Voltage VDDC -0.12 1.32 PLL Supply Voltage PLLVDD -0.12 1.32 IO Supply Voltage VDDO -0.33 3.63 Analog Supply Voltage AVDD -0.25...

  • Page 187: Thermal Data

    Preliminary Hardware Data Module BCM7405 Thermal Data 06/29/07 Ge ne ral In for mati o n HERMAL Thermal Data..........................1-174 Bro adco m Co rp or atio n Document 7405-1HDM00-R Page 1-173 2/24/2008 9T6WP...

  • Page 188: Table 1-43: Thermal Data (Without External Heat Sink, 2S2P Board)

    BCM7405 Preliminary Hardware Data Module Thermal Data 06/29/07 HERMAL Table 1-43: Thermal Data (Without External Heat Sink, 2s2p Board) Device power dissipation, P (W) Ambient air temperature, T (°C) θ in still air (°C/W) 11.19 θ (°C/W) 3.84 θ (°C/W) 3.98...

  • Page 189: Mechanical Characteristics

    Preliminary Hardware Data Module BCM7405 Mechanical Characteristics 06/29/07 Ge ne ral In for mati o n ECHANICAL HARACTERISTICS Mechanical Drawings ........................1-176 Bro adco m Co rp or atio n Document 7405-1HDM00-R Page 1-175 2/24/2008 9T6WP...

  • Page 190: Figure 1-54: 976-Fcbga+Hs Package (With Heat Sink)

    BCM7405 Preliminary Hardware Data Module Mechanical Characteristics 06/29/07 ECHANICAL RAWINGS Figure 1-54: 976-FCBGA+HS Package (With Heat Sink) Bro adco m C orp or atio n Page 1-176 Mechanical Drawings Document 7405-1HDM00-R 2/24/2008 9T6WP...

  • Page 191: Figure 1-55: 976-Fcbga+Hs Package (Without Heat Sink)

    Preliminary Hardware Data Module BCM7405 Mechanical Characteristics 06/29/07 Figure 1-55: 976-FCBGA+HS Package (Without Heat Sink) Bro adco m Co rp or atio n Document 7405-1HDM00-R Mechanical Drawings Page 1-177 2/24/2008 9T6WP...
  • Page 192 BCM7405 Preliminary Hardware Data Module Mechanical Characteristics 06/29/07 Bro adco m C orp or atio n Page 1-178 Mechanical Drawings Document 7405-1HDM00-R 2/24/2008 9T6WP...

  • Page 193: Ordering Information

    Preliminary Hardware Data Module BCM7405 Ordering Information 06/29/07 Ge ne ral In for mati o n RDERING NFORMATION Ordering Information ........................1-180 Bro adco m Co rp or atio n Document 7405-1HDM00-R Page 1-179 2/24/2008 9T6WP...

  • Page 194: Table 1-44: Ordering Information

    Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.

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