Arcam FMJ AV8 Service Manual page 62

Preamp processor
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L1100
P3V3D
70R@100MHz
7F004
C1101
C1104
100N 0805
100N 0805
DGND
DGND
IC1102
R1101
1
100R 0805 1%
MR
9
R1102
RCLK MCLK
CP
100R 0805 1%
3
2
DSP2 BCLK
D0
Q0
4
5
DSP2 LRCLK
D1
Q1
6
7
DATA LR
D2
Q2
11
10
DATA CS
D3
Q3
13
12
DATA LSRS
D4
Q4
14
15
DATA LSBRSB
D5
Q5
74LV174 D SM
DGND
R1100
PSU SYNC BCLK
PSU SYNC BCLK
100R 0805
L1101
P3V3D
70R@100MHz
IC1100
7F004
10
20
GND
VCC
1
C1100
C1103
1OE
19
100N 0805
100N 0805
2OE
RP1101
DGND
DGND
100R X 4 ISO
2
18
1
8
1A0
1Y0
DAC I2S BCLK LR
4
16
2
7
1A1
1Y1
DAC I2S BCLK CS
DGND
6
14
3
6
1A2
1Y2
DAC I2S BCLK LSRS
8
12
4
5
1A3
1Y3
DAC I2S BCLK LSBRSB
17
3
8
1
2A0
2Y0
DAC I2S LRCLK LR
15
5
7
2
2A1
2Y1
DAC I2S LRCLK CS
13
7
6
3
2A2
2Y2
DAC I2S LRCLK LSRS
11
9
5
4
2A3
2Y3
DAC I2S LRCLK LSBRSB
100R X 4 ISO
74LVC244AD
RP1100
CP1100
CP1101
100P X 4 ISO
100P X 4 ISO
DGND
RP1102
8
1
DAC I2S DATA LR
7
2
DAC I2S DATA CS
6
3
DAC I2S DATA LSRS
5
4
DAC I2S DATA LSBRSB
100R X 4 ISO
CP1102
100P X 4 ISO
DGND
DSP2 BCLK
DSP2 LRCLK
DATA LR
DATA CS
DATA LSRS
DATA LSBRSB
DRAWING TITLE
AV8 Reclocking
23425
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB5 9PB
SK1100
1
2
3
4
5
6
7
8
AMPCT8
DGND
SK1101
1
2
3
4
5
6
7
8
AMPCT8
DGND
02_E161 WAF
1/8/02
CHANGES TO SOME PHASE LOCKED LOOP COMPS AND IC907
02_E160 WAF
27/06/02
R921 FROM 10K TO 33K
Filename:
AVD RECLOCKING.SCH
02_E127 AD
27/06/02
Remove R803 for PLL board upgrade
Notes:
02_101
WF/AD
16/5/02
IC906 FROM 5G24LC08 TO 5G24LC16 TO GIVE MORE SPACE
C200, C201 & C228 changed from 10U 35V to 100U 16V R911 TO 10K
02_E044
WAF
12/02/02
R701 TO R704 & R708 TO R711 CHANGED TO 3K3 IC104 UPDATED
ECO No.
INITIALS
DATE
DESCRIPTION OF CHANGE
Sheet
Contact Engineer:
EngName A Dutton
Contact Tel:
(01223) 203200
Printed:
1-Aug-2002
1.6.0
1.5.0
1.4.0
1.3.0
1.2
ISSUE
11
of
11
DRAWING NO.
L896CT

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