Clock Generator - AMD D900K Service Manual

CLOCK GENERATOR

CKVDD
L31
1 2
+3VS
HCB-2012K-121T30
C588 C662 C612
C122 0.1UF
0.1UF 10UF(0805) 1UF(0603)
L37
1 2
+3VS
HCB-2012K-121T30
C671
C158
0.1UF 10UF(0805)
(5,12,20,27) SMBCLK
(5,12,20,27) SMBDATA
C614 C663
100PF(R) 100PF(R)
C129 22PF
C128 22PF
R136 10K
ALL_PWRGD RESET#
R130 0(R)
(3,10,11,13,31) ALL_PWRGD
+3VS
+3VS (8,9,10,11,12,13,14,15,16,19,20,21,22,24,25,27,29,31,32,33)
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U5
RP1
1 56
VDDA CPUCLK8T0
3 55
VDDREF CPUCLK8C0
C640 C661 C613 10 RP2
VDDPCI
0.1UF 0.01UF 0.01UF 16 53
VDDPCI CPUCLK8T1
20 52
VDD CPUCLK8C1
21 RP3
VDD48
26 47
VDDAGP PCIEXT0
39 46
VDDPCIEX PCIEXC0
45 RP4
VDDPCIEX
51 44
VDDCPU PCIEXT1
C652 C641 C159 43
PCIEXC1
0.1UF 0.01UF 0.01UF
2 42
GND PCIEXT2 T
8 41
GNDREF PCIEXC2 T
15
GNDPCI
19 38
GNDPCI PCIEXT3 T
24 37
GND48 PCIEXC3 T
30
GNDAGP
32 36
GNDPCIEX PCIEXT4 T
40 35
GNDPCIEX PCIEXC4 T
50
GND
54 34
GNDCPU PCIEXT5 T
33
PCIEXC5 T
SMBCLK
31 29
SCLK AGPCLK0
FS4
28
FS4/AGPCLK1
SMBDATA
48 27
SDATA AGPCLK2
FS2
R495 10K 9 11
+3VS
VTTPWRGD/PD# FS2/PCI0 FS3
12
FS3/PCI1
RESET#
25 13
RESET# PCI2
14
PCI3
R106 475_1% 49 17
IREF PCI4
18
PCI5
6
X1
FS0
4
FS0/REF0 FS1
X1 5
D04
FS1/REF1
14.31M
22
48MHz
7 23 48MHZSEL
X2 SEL24_48#/24_48MHz
ICS953201
+3VS
FS_[4:0] CPU PCIEX AGP PCI FS_[4:0] CPU PCIEX
00000 100.90 100.90 67.27 33.63 10000 100.00 100.00
00001 133.90 100.43 66.95 33.48 10001 133.00 100.00
00010 168.00 100.80 67.20 33.60 10010 166.66 104.16
00011 202.00 101.00 67.33 33.67 10011 200.00 100.00
00100 100.20 100.20 66.80 33.40 10100 103.00 103.00
00101 133.50 100.13 66.75 33.38 10101 137.33 103.00
00110 166.70 100.02 66.68 33.34 10110 171.66 103.00
00111 200.40 100.20 66.80 33.40 10111 206.00 103.00
01000 160.00 100.00 66.67 33.33 11000 208.00 104.00
01001 202.00 101.00 67.33 33.67 11001 210.00 105.00
01010 210.00 105.00 70.00 35.00 11010 215.00 107.50
01011 212.00 106.00 70.67 35.33 11011 220.00 110.00
01100 270.00 101.25 67.50 33.75 11100 226.00 113.00
01101 225.00 112.50 75.00 37.50 11101 230.00 115.00
01110 266.67 100.00 66.67 33.33 11110 240.00 120.00
01111 300.00 112.50 75.00 37.50 11111 250.00 125.00
Clock Synthesizer
PECLK_NB
PECLK_NB#
SRCCLK_VGA
SRCCLK_VGA#
4P2R-15(0402)
CPUCLK
1 4
CPUCLK (3)
CPUCLK#
2 3
CPUCLK#(3)
4P2R-15(0402)
HCLK
1 4
HCLK (10)
HCLK#
2 3
HCLK# (10)
4P2R-15(0402) Place these components close to their
SRCCLK_VGA
1 4
SRCCLK_VGA(14)
SRCCLK_VGA# respective series damping resistor of
2 3
SRCCLK_VGA#(14)
4P2R-15(0402)
the clock ouput.
PECLK_NB
1 4
PECLK_NB(9)
PECLK_NB#
2 3
PECLK_NB#(9)
FS0
FS_0
FS1
FS_1
FS2
FS_2
FS3
FS_3
FS4
FS_4
VCLK_NB
R126 22
VCLK_NB (10)
VCLK_SB
R127 22 R129
VCLK_SB (13)
PCLK_FWH
R505 22
PCLK_FWH(22)
PCLKSIO
R107 22 8.2K(R)
PCLKSIO(22)
PCLKLAN
R108 22
PCLKLAN (20)
PCLK1394
R111 22
PCLK1394 (19)
PCLKH8
R112 22
PCLKH8 (24)
PCLKPCM
R113 22
PCLKSB PCLKPCM(17)
R117 22
Place these components close to their
PCLKMINI1 PCLKSB (13)
R510 22
PCLKMINI1 (29)
PCLKMINI2 respective series damping resistor of the
R114 22
PCLKMINI2 (29)
APICCLK
R485 22
clock ouput.
APICCLK(13)
SIO_OSC
R102 22
SIO_OSC(12)
CODECCLK14
R103 22
CODECCLK14 (25)
Set FS_[4:0] value at 10011 for
USBCLK48
R118 33
USBCLK48(11)
SIOCLK48 default frequencies as below:
R131 22
SIOCLK48(22)
CPU
200.00
PCLKSB
USBCLK48
SIOCLK48
PCLKLAN
PCLK1394
PCLKH8
AGP PCI
PCLKPCM
66.67 33.33
SIO_OSC
66.67 33.33
PCLKMINI1
69.44 34.72
PCLKSIO
66.67 33.33
PCLKMINI2
68.67 34.33
VCLK_NB
68.66 34.33
VCLK_SB
68.66 34.33
68.67 34.33
69.33 34.67
CPUCLK
70.00 35.00
CPUCLK#
71.67 35.83
HCLK
73.33 36.67
HCLK#
75.33 37.67
76.67 38.33
80.00 40.00
83.33 41.67
Schematic Diagrams
R105 49.9_1%
R110 49.9_1%
R496 49.9_1%
R506 49.9_1%
Sheet 2 of 40
CLOCK
GENERATOR
48MHZSEL
R132 10K
+3VS
R481 10K
R482 10K
R491 10K(R)
R492 10K(R)
R128 10K
R494 R493 R484 R483
8.2K 8.2K 8.2K(R) 8.2K(R)
PCIEX AGP PCI
100.00 66.67 33.33
C659 10PF(R)
C660 10PF(R)
C670 10PF(R)
C611 10PF(R)
C638 10PF(R)
C639 10PF(R)
C649 10PF(R)
C595 10PF(R)
C651 10PF(R)
C610 10PF(R)
C650 10PF(R)
C984 10PF
C985 10PF
D04
C589 10PF(R)
C596 10PF(R)
C597 10PF(R)
C615 10PF(R)
CLOCK GENERATOR B - 3