LG CJ65 Service Manual page 38

5. NO SOUND
There is no sound output in the CD FUNCTION, repair the set according to the following guide.
5-1. IN THE CD FUNCTION
5-1-1. Solution
Please check and replace IC501, IC601 on MAIN board.
5-1-2. How to troubleshoot (Countermeasure)
1) Check CD_BCLK, CD_LRCK, & CD_DOUTA signals from IC401 to IC500.
  If no signal, check if the RF & servo signals from MD is entered to IC401.
Refer to the "No operation of MD" guide on Item 4.
2) Check the following I2S signal flow. < I2S audio signal Interface >
- ADC_BCK : IC500_Pin E1 --> IC700_Pin23
- ADC_LRCK : IC500_Pin D1 --> IC700_Pin22 (44.1 kHz)
- MIX_DATA_0 : IC500_Pin E2 --> IC700_Pin24
- MIX_DATA_1 : IC500_Pin R2 --> IC700_Pin25
- ADC_MCLK : IC500_Pin D2 --> IC700_Pin44
  If there is any trouble, check the power for each IC. The power is normal but, if the signal waveform to
the IC is distorted or no signal, replace it with a new one.
3) Check if "Digital audio AMP block" on Item 5-2 is normal.
5-1-3. Service hint (Any picture / Remark)
P/UP
IC401
M
12.288 MHZ
PWM
TAS5548
< I2S Signal Flow >
ONE POINT REPAIR GUIDE
DSP IC500
176 PIN
BGA
Audio DSP-1
USB 2.0 OTG
SRAM29KB
Main Processor DSP
Audio DSP-0
I-Cache 8KB
USB 1.1 133Mhz
16KB
SRAM29KB
ARM DSP
Host/Device
I-Cache D-Cache 8KB
926EJS
I-Cache 8KB
133Mhz
16KB
400Mhz
SRAM (10K)
D-Cache 8KB
D-Cache
I2S (7.1ch)
SDRAM
Controller Boot ROM (20KB) GDMA 2ch
SPDIF (Rx, Tx)
Interrupt
ADPCM
controller
CDROM x8 speed
Decoder PLL
ADC (12bit*5ch) RTC & Wake up
GDMA 3ch Clock Controller
Timer, Watchdog UART 4ch (Max)
Reset Controller
NAND Controller GPIO (72 Max) I2C 2ch
within BCH codec
Test Controller
14bits ECC SPI 4ch (Max) SDHC-SDIO 4ch (Max)
FR,FL
TAS5624LA
< Waveform of I2S audio interface signals >
3-11
MCS_MCLK (16.93 MHz)
MCS_BCK(1.4 MHz)
MCS_DATA_OUT
MCS_LRCK(44.1 KHz)