Related Manuals for Caen V1729
Summary of Contents for Caen V1729
- Page 1 Technical Information Manual Revision n. 3 22 June 2005 MOD. V1729 4 CHANNEL/12BIT SAMPLING ADC MANUAL REV.3 NPO: 00109/04:V1729.MUTx/03...
- Page 2 User. It is strongly recommended to read thoroughly the CAEN User's Manual before any kind of operation. CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice.
-
Page 3: Table Of Contents
PRELIMINARY Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 TABLE OF CONTENTS GENERAL DESCRIPTION........................5 .............................5 VERVIEW ..........................6 AMPLING FREQUENCY ......................6 NPUT SIGNALS YNAMIC RANGE OPERATING MODES ..........................7 ..............7 EFINITION OF THE ACQUISITION WINDOW RIGGER MODES 2.1.1... -
Page 4: List Of Figures
PRELIMINARY Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 LIST OF FIGURES . 1.1: ........................5 DATA FLOW IN THE BOARD . 2.1: .................7 CHRONOGRAM OF THE STOPPING OF THE ACQUISITION . -
Page 5: General Description
22/06/2005 1. General description Overview The CAEN Mod. V1729 board is suited for acquisition of fast analog signals based on the MATACQ (analog matrix) chip developed by collaboration of the CEA/DAPNIA and the l’IN2P3/LAL [1]. The V1729 board, in the mechanical format VME double Europe, is compatible with several standards of acquisition (VME A32/D32, A24/D16, and GPIB). -
Page 6: Sampling Frequency
22/06/2005 Sampling frequency The V1729 board is sequenced by an oscillator at a frequency of 100MHz. No greater frequency signal exists on the board. This is what explains the low consumption of the system. The sampling at a very high frequency (Fe) in the MATACQ chip is in fact realized by virtual multiplication of frequency inside the chip by a factor up to 20. -
Page 7: Operating Modes
PRELIMINARY Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 2. Operating modes Definition of the acquisition window. Trigger modes 2.1.1 Principle, PRETRIG, POSTTRIG During the acquisition, the analog signal is continuously sampled in the analog memory which is comparable to a circular buffer with a depth of 2560 points (time depth = 2560/Fe). -
Page 8: Trigger Sources
2.1.4 TRIGOUT signal A copy of the pre-trigger signal (positive pulse) generated by the V1729 board is available at the output on a LEMO plug on the front panel (TRIG_OUT output on the NIM level). It can in particular permit synchronization of trigger for several boards. -
Page 9: Validation Of The Trigger By A Second Subsequent Signal
PRELIMINARY Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 DAC threshold EnCh0 In italics with arrows : front panel signals. EnCh1 TRIG enable EnCh2 EXT EN TRIG TRIG_OUT EnCh3 TRIGA... -
Page 10: Dead Time At Restarting Of The Acquisition; Pretrig
Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 Fig. 2.4: simplified description of the trigger validation system. Dead time at restarting of the acquisition; Pretrig The frequency of the clock present on the board is relatively low (50MHz or 100MHz). In order to be able to sample at a rate equal to or greater than the Giga-sample per second, the MATACQ chips realize a virtual multiplication of frequency. -
Page 11: Correction Of Data
PRETRIG. - The program then waits for a request emitted by the V1729 board when the data are ready to be read. For this, there exist two possibilities illustrated by Fig 2.5 : Waiting and handling of an interruption (SRQ in GPIB, IRQ3 in VME). -
Page 12: Correction Of The Pedestals
PRELIMINARY Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 Send RESET BOARD Board Parameters Initialization Send START ACQUISITION Trigger auto ? Wait for end of PRETRIG Send SOFT TRIGGER Wait for REQUEST Read Data: •... -
Page 13: Temporal Corrections
PRELIMINARY Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 Read INTERRUPT REGISTER Asynchronous Interrupt detected by hardware (IRQ3 or SRQ) Bit 0 =1 Interrupt request acknowledge => clear INTERRUPT REGISTER Interrupt request acknowledge =>... -
Page 14: Fig. 2.7: Unfolding Of The Circular Memory
PRELIMINARY Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 1.1.1.1.1.1.1.1 1.1.1.1.1.1.1.2 Writing direction trigger cell … cell i cell 1 cell … CIRCULAR BUFFER cell 0 cell … cell cell n -1... - Page 15 Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 Where: dT is the sampling period (500ps or 1ns) DT0 is a fixed temporal offset, close to 0, due to signal propagation times in the board (of which the calibration is described in 3.1.1)
-
Page 16: Synchronizations And Calibrations
PRELIMINARY Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 3. Synchronizations and calibrations Synchronization between the channels 3.1.1 Channels from the same board A single trigger signal is used for all of the channels from the same board. The acquisition of these channels will therefore naturally be synchronous, with a typical jitter of only 20ps RMS. -
Page 17: Calibrations
MATACQ chips and the RAM, or at the beginning of the acquisition phase). Its transition to 0 indicates then that the board is now ready to record a signal. Calibrations In order to attain the optimal metrological performance, the V1729 board requires calibrations. These remain valid for several weeks, even several months. 3.3.1 Calibration of the interpolator The temporal interpolator (vernier) requires a calibration. -
Page 18: Fig. 3.1: Diagram Of The Calibration Of The Verniers
PRELIMINARY Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 Send RESET BOARD Board parameters initialization Set PRETRIG=POSTRIG=1 Send START ACQUISITION Trigger auto ? Send SOFT TRIGGER Wait for request Read vernier data only Calculate MINVER &... - Page 19 PRELIMINARY Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 StartAcq(); Wait(); GetVernier(vernier); //fwrite(vernier,sizeof(vernier),1,Fvernier); for (i=0;i<V1729_VERNIER_DEPH;i++){ sprintf(s,"%d\n",vernier[i]); fwrite(s,1,strlen(s),Fvernier);} printf("Vernier results saved\n"); void TCAENADC::GetVernier(unsigned short *vernier) printf("TCAENADC::GetVernier()\n"); unsigned short buffer[V1729_VERNIER_DEPH]; int readed;...
-
Page 20: Calibration Of The Pedestals
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 3.3.2 Calibration of the pedestals For this, a calibration of the baselines is necessary. This operation will be necessary following all changes either in the frequency of sampling, or in the bandwidth of the write amplifier (BWL), or in the read modes (FAST READ MODES). -
Page 21: Technical Specifications
The Model V1729 is housed in a one unit standard VME unit. Sampling frequency The V1729 board is sequenced by an oscillator at Fp frequency. No greater frequency signal exists on the board. This is what explains the low consumption of the system. The sampling at a very high frequency (Fe) in the MATACQ chip is in fact realized by virtual multiplication of frequency inside the chip by a factor up to 20. -
Page 22: Front Panel
PRELIMINARY Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 Front panel Mod. V1729 +8 TO 12 V -8 TO 12 V GPIB RESET CLOCK BUSY ACQRUNNING TRIG WR-RAM INTERRUPT GPIB... -
Page 23: Mechanical And Electrical Standards
Fig. 4.2: implementation of the connectors and configuration elements on the V1729 The V1729 board is of VME 6U mechanical format. The two connectors P1 and P2 of the VME crate are usable, both for the supply and the VME dialogue. However, these boards can completely be accessed via the GPIB bus out of a VME crate, or by only using the latter as mechanical and power supply support. -
Page 24: Summary Of Front Panel Signals
The fast logical signals of input “EXT_TRIG” and of output “BUSY/SYNC_OUT” and “TRIG_OUT” of the V1729 board use the NIM standard (-16mA in 50 Ohms for the logical state « 1 », no current for the logical state « 0 »). -
Page 25: Supplies
4.5.4 Supplies The V1729 board uses the standard supplies of the VME : +/-12V and +5V. It fabricates the –5V for the ECL logics starting from the +5V with the help of a DC- DC converter capable of delivering 600mA. -
Page 26: Straps And Resistor Network Sockets
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 4.5.6 Straps and resistor network sockets A certain number of sockets for straps and resistor networks are available on the board. These are their respective roles:... -
Page 27: Using A Shifted Input Range
Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 4.5.8 Using a shifted input range The input signal range is defined by default to be +/-0.5V. In order to shift it, one has to make use of free CMS-805 foot-prints located around the M3 amplifier (LM4130), itself located between the MATACQ chip and the ADC (ADS803E). -
Page 28: Interfaces
VME standard). 4.6.2 GPIB Interface The V1729 boards can have an address set between 0 and 29 (decimal). Writing The GPIB commands are carried out by writing a string of characters in the board situated at the address designated by the rotary switches. -
Page 29: Reading Of The Data In The Ram, Mapping
MSByte, LSByte. Interruption At the end of the emptying of the data in the RAM, the V1729 board generates a « Service Request (SRQ)» on the GPIB bus. The board is not compatible with the PARALLEL or SERIAL POLLING protocols. However the GPIB controller can identify the SRQ emitor by sequentially scanning the INTERRUPT registers of the different boards. - Page 30 Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 If the number of columns to read (register NB OF COLS TO READ) chosen is less than 128 (default value), the transfer in RAM will stop as soon as this number has been reached.
-
Page 31: List Of The Sub-Addresses
Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 List of the sub-addresses The table of the sub-addresses corresponding to the different commands is presented below. A certain number among them are reserved for expert usage. They are indicated by the word «... - Page 32 Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 The sub-addresses are organized by type. For more detail on their specific use in VME or GPIB, refer to 4.6. The functions of these different commands and registers are described below : RESET BOARD : reset of the board.
- Page 33 PRELIMINARY Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 Bits Function Val = 0 => SOFTWARE TRIGGER Val = 1 => trigger on discriminator (threshold fixed by the DAC) Val = 2 => external trigger from the TRIG_EXT input Val = 3 =>...
- Page 34 FPGA. The 3 MSbits give the type of board and the 5 LSbits the version number of the firmware stored in the PROM. The code corresponding to the V1729 board is 3, which gives a root number of h60 for FPGA VERSION.
-
Page 35: Synopsis Of The Board
100MHz Fig. 4.3: synopsis of the V1729 board The architecture of the V1729 board (Fig 4.3) is modulary. This architecture as well as the components used were selected so as to minimize the costs of conception and production of the board. The board is principally made up of six blocks : The 4 channels of acquisition and fast digitization (synopsis of a channel in Fig 4.4). -
Page 36: Fig . 4.4: Synopsis Of An Acquisition Channel On The
PRELIMINARY Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 The different logical level transfers present on the board are not represented in the synopsis. Conversion : unipolar Register -> Filter... -
Page 37: Specifications And Performances
Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 5. Specifications and performances The following table summarizes the MAIN specifications and performances of the V1729: Input analog signals Number of channels Input impedance 50 Ohms Dynamic Range +/- 0.5V... -
Page 38: Bibliography
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 6. BIBLIOGRAPHY [1] E. Delagnes, D. Breton, Echantillonneur analogique rapide à grande profondeur mémoire. French patent n°01 05607 from April 26th 2001. US Patent 6,859,375 from February 22nd 2005 : Fast analog sampler with great memory depth.