Dv-Board Schematic Diagram - Panasonic TX-32LXD500 Service Manual

11.15. DV-Board Schematic Diagram

DV-BOARD TXNDV10LLM
A
C5004
10V
1u
B
JAE
K1FA119D0001
JK5001
G D5013
D4ED13900001
G
1
D2+
2 D2G L5015
J0MAB0000176 D5014
3 D2-
D4ED13900001
4 D1+
5 D1G
6 D1- L5016
D5015
D4ED13900001
7 J0MAB0000176
D0+
8 D0G
9
D0-
D5016 D4ED13900001
10 CLK+
11 CLKG
12 CLK- D5017
L5017
D4ED13900001
13 CEC J0MAB0000176
14
C
15 D5018
SCL D4ED13900001
16 DDC DATA
17
DDCG
18 +5V
L5018 D5019
19 HPDT
J0MAB0000176 D4ED13900001
DDC_SCL
D5020
D4ED13900001
DDC_SDA
R5176
0 HOTPLUG
L5002
J0JHC0000045
R5196
10k
C5134 C5001
0.1u 16V
16V 4.7u
R5006
1k
D
TP5002
R5013
47k
R5011
0
R5007
0 G1
1
D5023 D5022
D4ED13900001
D4ED13900001
E
F
TX-26/32LXD500 TX-26/32LX500F/P
DV-Board Schematic Diagram
1 2
MAIN5V
TP5000
C5005
16V
0.1u
5V_MAIN
R5025 22 3.3V_SCL
R5024 22
3.3V_SDA
RXC-
RXC+
RX0-
RX0+
RX1-
RX1+
RX2-
RX2+
C5018
0.1u
16V
C5017
C5019
1u
1000p
10V
50V
D5025
MAZ30560ML
D5021
D4ED13900001
R5014 R5015
4.7k
4.7k
D1 6 4 D2
*Q5001
G2
B1MBACA00008
3 R5019
S1 5 2 S2 47
3.3V_SCL
R5022
3.3V_SDA
1k
*Q5002
2SD0601A0L
FOR DDC RESET R5020
100k
*R5021
10k
CABLE IN -> Hi : Norm
CABLE OUT -> Low : Mute
*Q5003
*R5017
39k 2SD0601A0L
R5018
10k for Audio MUTE and 5Vdet
Hi : MUTE
Low : Detect HPD5V
3 4
MAIN3.3V
L5003
J0JHC0000045
C5013
R5034
16V
0
4.7u
L5007
J0JHC0000045
R5040 R5356
R5354
EXB38V330JV
C5133
33 33
16V
1.5V_MAIN
C5046 4.7u
50V C5030 R5366
470p 16V 4.7k
0.1u
C5016 C5047
R5033 C5014 C5034
0.1u
0.1u 0.1u
16V
16V
0 0.1u 16V 16V
C5136
C5137
10V 50V
1u 1000p
0 0
97 64
3.2 0
98 63
3.2 0
99 62
3.2 0
100 61
P1RXCM Q22
EXTCKIN HSYNC
0 101 60 0
AVSS VSS VDD15 Q21
3.2 0
102 P1RXCP FLT DE 59
Q20
3.2 0
103 58
P1RX0M VSS
0 0
104 AVSS 57
Q19
3.2 0
105 P1RX0P 56
Q18
3.2 0
106 P1RX1M Q17 55
0 0
107 AVSS 54
Q16
3.2 3.2
108 53
P1RX1P VDD33
0.2 0
109 52
P1RX2M Q15
0 0
110 AVSS 51
Q14
3.2 0
111 P1RX2P 50
Q13
3.2 IC5003 0
112 AVDD 49
Q12
3.2 0
113 AVDD 48
VSS
3.2 114 P0RXCM MN864721 47 0
Q11
0 0
115 AVSS 46
Q10
3.2 0
116 P0RXCP 45
HDMI I/F Q9
3.2 0
117 P0RX0M 44
Q8
0 3.2
118 AVSS 43
VDD33
3.2 0
119 P0RX0P Q7 42
3.2 0 C5044
120 P0RX1M 41
Q6
16V
0 0
121 AVSS 40
Q5 0.1u
3.2 122 39 0
P0RX1P Q4
3.2 0
123 P0RX2M 38
VSS
LPSA5 VSS
0 0
124 AVSS 37
LPSA6 VDD15 Q3
3.2 0
125 LPSA7 TRST 36
P0RX2P Q2
3.2 0
126 35
3.2 0
127 34
0 128 33 3.2
C5040
0.1u
16V
C5039
C5036
R5037
16V
10k 16V
0.1u
0.1u
R5038
R5030 10k C5020
10k 16V
0.1u
TP5022
from H90 DAC
High level = 1V
0
C5135
10V
1u
R5023
68
5 6
49
TX-32LXD500 / TX-26LXD500 / TX-32LX500F / TX-32LX500P / TX-26LX500F / TX-26LX500P
L5021
TP5006
J0JHC0000045
C5054 C5056 C5057
16V 16V 50V
4.7u 0.1u 100p
C5140 1.5 3.2
10V IC5015
TP5001
Vout Vin
1u
C0CBCAD00016
GND
Np Vcont
R5335
AVR+1.5V
33 1.2 0 3.2
AP_DE
RX_SD0#
C5143 C5141
1000p 10V
1u
50V
RX_WS
*L5022
RX_SCK
J0JCC0000166
CLKINB2
<
*R5336
56 YGIN9 RX_MCLK
YGIN8
YGIN7
YGIN6 NIRQ2
R5399
1.8k
YGIN5
HDMI_5V_DET
YGIN4 TP5020
R5376 100
YGIN3
YGIN2
HPD
C5049
R5334
D1HG5608A002
16V
56
UBIN9
0.1u TP5011
JTAG_TRST
UBIN8
TP5012
UBIN7 JTAG_TDO
UBIN6
TP5013
JTAG_I_TDO
UBIN5
UBIN4 JTAG_TCK
UBIN3
TP5015
JTAG_TMS
UBIN2
R5367
D1HG5608A002
HDMI_RST
56
UBIN1
R5369 56 UBIN0
R5370 56
SCL0B
SDA0B
R5371 56
YGIN1
56 YGIN0
R5372
HDMIINT
*ZA5002
TESA169
ZA5003
R5391 TESA169
47k
C5144
16V 0.1u
*IC5017
C3EBFC000037
DDC EEPROM
0 3.2
1 A0 8
VCC
Q5004
TP5007
0.3
2SC584500L 0 3.1
2 A1 7
WP
3.2
R5396
100
TP5008
0 3 A2 6 3.2
SCL
R5394
22 TP5009
0 4 VSS 5 3.2
SDA
R5395
22
TP5010
TX-26/32LXD500 TX-26/32LX500F/P
DV-Board Schematic Diagram
7 8
TP5017
TP5025
60
30
VSIB
59
29 HSIB
58
28 AP_DE
57
27
56
26 CLKINB2
55
25
54
24 YGIN9
53
23
YGIN8
52
22 YGIN7
51
21 YGIN6
50
20
YGIN5
49
19
48
18
YGIN4
47
17 YGIN3
46
16
YGIN2
45
15 UBIN9
44
14 UBIN8
43
13
42
12 UBIN7
41
11
TP5014 UBIN6
40
10 UBIN5
39
9
TP5018 UBIN4
38
8 UBIN3
37
7 UBIN2
36
6
TP5023
35
5 UBIN1
TP5024
34
4
UBIN0
33
3 YGIN1
32
2
YGIN0
31
1
ZA5001
*DV15
K4CD01000011
TO
*ZA5005
DG-BOARD
K4CD01000011
(DG10)
SUFFIX JW
AE
*JS5004
9