Table of Contents
Advertisement
Quick Links
PRODUCT FEATURES
Available in a 36-pin lead-free RoHS compliant (6 x 6
x 0.90mm) QFN package
Interface compliant with the UTMI specification
(60MHz, 8-bit bidirectional interface)
Only one required power supply (+3.3V)
USB-IF "Hi-Speed" certified to USB 2.0 electrical
specification
Supports 480Mbps Hi-Speed (HS) and 12Mbps Full
Speed (FS) serial data transmission rates
Integrated 45Ω and 1.5kΩ termination resistors
reduce external component count
Internal short circuit protection of DP and DM lines
On-chip oscillator operates with low cost 24MHz
crystal
Latch-up performance exceeds 150mA per EIA/JESD
78, Class II
ESD protection levels of 5kV HBM without external
protection devices
SYNC and EOP generation on transmit packets and
detection on receive packets
NRZI encoding and decoding
Bit stuffing and unstuffing with error detection
Supports the USB suspend state, HS detection, HS
Chirp, Reset and Resume
Support for all test modes defined in the USB 2.0
specification
55mA Unconfigured Current (typical) - ideal for bus
powered applications.
83uA suspend current (typical) - ideal for battery
powered applications.
Industrial Operating Temperature -40
SMSC USB3280
USB3280
Hi-Speed USB Device
PHY with UTMI Interface
Applications
The USB3280 is the ideal companion to any ASIC, SoC
or FPGA solution designed with a UTMI Hi-Speed USB
device (peripheral) core.
The USB3280 is well suited for:
Cell Phones
MP3 Players
Scanners
External Hard Drives
Digital Still and Video Cameras
Portable Media Players
Entertainment Devices
Printers
o
o
C to +85
C
DATASHEET
Datasheet
Revision 1.5 (11-15-07)
Advertisement
Table of Contents
Subscribe to Our Youtube Channel
Related Manuals for SMSC USB3280
Summary of Contents for SMSC USB3280
-
Page 1: Product Features
SMSC USB3280 USB3280 Hi-Speed USB Device PHY with UTMI Interface Applications The USB3280 is the ideal companion to any ASIC, SoC or FPGA solution designed with a UTMI Hi-Speed USB device (peripheral) core. The USB3280 is well suited for: Cell Phones... - Page 2 Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.
-
Page 3: Table Of Contents
Chapter 9 Package Outline ........... 42 SMSC USB3280 DATASHEET Revision 1.5 (11-15-07) - Page 4 Figure 8.9 USB3280 Application Diagram........
- Page 5 Table 8.10 Attach and Reset Timing Values ..........40 SMSC USB3280 Revision 1.5 (11-15-07)
-
Page 6: Chapter 1 General Description
Chapter 1 General Description The USB3280 provides the Physical Layer (PHY) interface to a USB 2.0 Device Controller. The IC is available in a 36-pin lead-free RoHS compliant QFN package. Product Description The USB3280 is an industrial temperature USB 2.0 physical layer transceiver (PHY) integrated circuit. -
Page 7: Chapter 2 Functional Block Diagram
Recovery Unit Conversion Clock Bit Unstuff Data NRZI Recovery Decode Elasticity Buffer BIASING Bandgap Voltage Reference Current Reference Figure 2.1 USB3280 Block Diagram DATASHEET System Clocking 1.5kΩ FS SE+ FS SE- FS RX HS RX HS SQ Revision 1.5 (11-15-07) -
Page 8: Chapter 3 Pinout
XCVRSELECT TERMSELECT TXREADY SUSPENDN TXVALID RESET VDD3.3 Figure 3.2 USB3280 Pinout - Bottom View The flag of the QFN package must be connected to ground. Revision 1.5 (11-15-07) Hi-Speed USB Device PHY with UTMI Interface USB2.0 USB3280 PHY IC Figure 3.1 USB3280 Pinout - Top View... -
Page 9: Chapter 4 Interface Signal Definition
OPMODE[1:0] Input (OM1) (OM0) LINESTATE[1:0] Output (LS1) (LS0) SMSC USB3280 Table 4.1 System Interface Signals ACTIVE LEVEL High Reset. Reset all state machines. After coming out of reset, must wait 5 rising edges of clock before asserting TXValid for transmit. -
Page 10: Table 4.2 Data Interface Signals
USB Negative Data Pin. ACTIVE LEVEL External 1% bias resistor. Requires a 12kΩ resistor to ground. Used for setting HS transmit current level and on-chip termination impedance. External crystal. 24MHz crystal connected from XI to XO. DATASHEET Datasheet DESCRIPTION SMSC USB3280... -
Page 11: Table 4.5 Power And Ground Signals
REG_EN Input (REN) VDD1.8 (V18) (GND) VDDA1.8 (V18A) SMSC USB3280 Table 4.5 Power and Ground Signals ACTIVE LEVEL DESCRIPTION 3.3V Supply. Provides power for USB 2.0 Transceiver, UTMI+ Digital, Digital I/O, and Regulators. High On-Chip 1.8V regulator enable. Connect to ground to disable both of the on chip (VDDA1.8 and VDD1.8) regulators. -
Page 12: Chapter 5 Limiting Values
EIA/JESD 78, Class II CONDITIONS CONDITIONS XO driven by the external clock; and no connection at XI XO driven by the external clock; and no connection at XI DATASHEET Datasheet UNITS -0.3 -0.3 -0.3 -0.3 ±5 UNITS DD3.3 DD3.3 UNITS (±100ppm) SMSC USB3280... -
Page 13: Chapter 6 Electrical Characteristics
Low-Level Output Voltage High-Level Output Voltage Input Leakage Current Pin Capacitance Cpin Note 6.2 = 3.0 to 3.6V; V DD3.3 SMSC USB3280 (Note 6.1) CONDITIONS Device Unconfigured FS idle not data transfer FS current during data transmit FS current during data... -
Page 14: Table 6.3 Dc Electrical Characteristics: Analog I/O Pins (Dp/Dm) (Note 6.3)
| V(DP) - V(DM) | DIHS CMHS Squelch Threshold HSSQ Unsquelch Threshold 45Ω load HSOL DATASHEET Hi-Speed USB Device PHY with UTMI Interface Datasheet (Note 6.3) UNITS 0.050 0.150 Ω 40.5 49.5 MΩ 0.900 1.24 1.575 kΩ 1.425 2.26 3.09 kΩ SMSC USB3280... -
Page 15: Table 6.4 Dynamic Characteristics: Analog I/O Pins (Dp/Dm) (Note 6.4)
Requirements High Speed Mode Timing Receiver Waveform Requirements Data Source Jitter and Receiver Jitter Tolerance Note 6.4 = 3.0 to 3.6V; V DD3.3 SMSC USB3280 CONDITIONS 45Ω load HSOH 45Ω load OLHS HS termination resistor CHIRPJ disabled, pull-up resistor connected. 45Ω load. -
Page 16: Driver Characteristics Of Full-Speed Drivers In High-Speed Capable Transceivers
Driver Characteristics of Full-Speed Drivers in High-Speed Capable Transceivers The USB3280 uses a differential output driver to drive the USB data signal onto the USB cable. Figure 6.1 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiveron page 17 shows the V/I characteristics for a full-speed driver which is part of a high-speed capable transceiver. -
Page 17: Figure 6.1 Full-Speed Driver Voh/Ioh Characteristics For High-Speed Capable Transceiver
Figure 6.1 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver Drive Low Slope = 1/40.5 Ohm (mA) Test Limit 10.71 * |V Figure 6.2 Full-Speed Driver VOL/IOL Characteristics for High-speed Capable Transceiver SMSC USB3280 Slope = 1/49.5 Ohm Test Limit 0.566*V 0.698*V (Volts) Slope = 1/49.5 Ohm 1.09V... -
Page 18: High-Speed Signaling Eye Patterns
‘templates’. The two templates that are relevant to the PHY are shown below. TP1 TP2 USB Cable Traces Traces Transceiver Transceiver Connector Connector Hub Circuit Board Device Circuit Board Figure 6.3 Eye Pattern Measurement Planes Revision 1.5 (11-15-07) SMSC USB3280 DATASHEET... -
Page 19: Figure 6.4 Eye Pattern For Transmit Waveform And Eye Pattern Definition
Point 2 Point 3 300mV Point 4 300mV Point 5 -300mV Point 6 -300mV SMSC USB3280 defines the transmit waveform requirements for a hub (measured at TP2 Point 3 Point 4 Point 2 Point 1 Point 5 Point 6 Unit Interval 100% 7.5% UI... -
Page 20: Figure 6.5 Eye Pattern For Receive Waveform And Eye Pattern Definition
Point 3 Point 4 Point 2 Point 1 Point 6 Point 5 DATASHEET Datasheet 400mV Differential 0 Voltｓ Differential -400mV Differential 100% TIME (% OF UNIT INTERVAL) 15% UI 85% UI 35% UI 65% UI 35% UI 65% UI SMSC USB3280... -
Page 21: Chapter 7 Functional Overview
Hi-Speed USB Device PHY with UTMI Interface Datasheet Chapter 7 Functional Overview Figure 2.1 on page 7 shows the functional block diagram of the USB3280. Each of the functions is described in detail below. Modes of Operation The USB3280 supports an 8-bit bi-directional parallel interface. -
Page 22: Clock And Data Recovery Circuit
FS or HS rate, the data to the FS/HS TX block to be transmitted on the USB cable. Data transmit timing is shown in Figure 7.3 Transmit Timing for a Data Packet Revision 1.5 (11-15-07) Hi-Speed USB Device PHY with UTMI Interface Figure 7.3. DATASHEET Datasheet Figure 7.1 also shows SMSC USB3280... -
Page 23: Rx Logic
After the SIE asserts TXVALID it can assume that the transmission has started when it detects TXREADY has been asserted. The SIE must assume that the USB3280 has consumed a data byte if TXREADY and TXVALID are asserted on the rising edge of CLKOUT. -
Page 24: Figure 7.5 Receive Timing For A Handshake Packet (No Crc)
In the RX Wait state the receiver is always looking for SYNC. The USB3280 asserts RXACTIVE when SYNC is detected (Strip SYNC state). The USB3280 negates RXACTIVE when an EOP is detected and the elasticity buffer is empty (Strip EOP state). -
Page 25: Figure 7.6 Receive Timing For Setup Packet
FS LINESTATE. For HS mode support, the FS/HS RX block contains a squelch circuit to insure that noise is never interpreted as data. SMSC USB3280 DATASHEET Revision 1.5 (11-15-07) -
Page 26: Usb 2.0 Transceiver
USB 2.0 Transceiver The SMSC Hi-Speed USB 2.0 Transceiver consists of the High Speed and Full Speed Transceivers, and the Termination resistors. 7.6.1 High Speed and Full Speed Transceivers The USB3280 transceiver meets all requirements in the USB 2.0 specification. -
Page 27: Bias Generator
7.8.3 Reset Pin The UTMI+ Digital can be reset at any time with the RESET pin. The RESET pin of the USB3280 may be asynchronously asserted and de-asserted so long as it is held in the asserted state continuously for a duration greater than one CLKOUT cycle. The RESET input may be asserted when the USB3280 CLKOUT signal is not active (i.e. -
Page 28: Chapter 8 Application Notes
The HS receiver is used to detect Chirp J or K, where the output of the HS receiver is always qualified with the Squelch signal. If squelched, the output of the HS receiver is ignored. In the USB3280, as an alternative to using variable thresholds for the single-ended receivers, the following approach is used. -
Page 29: Opmodes
(the transceiver is transmitting a packet), in order to flag a transmission error. In this case, the USB3280 has already transmitted the SYNC pattern so upon negation of TXVALID the EOP must also be transmitted to properly terminate the packet. Changing the OPMODE[1:0] signals under all other conditions, while the transceiver is transmitting or receiving data will generate undefined results. -
Page 30: Se0 Handling
Revision 1.5 (11-15-07) DESCRIPTION 0 (reference) HS Reset T0 + 3. 0ms < T1 < HS Reset T0 + 3.125ms T1 + 100µs < T2 < T1 + 875µs DATASHEET Hi-Speed USB Device PHY with UTMI Interface Datasheet VALUE SMSC USB3280... -
Page 31: Suspend Detection
Resume signaling. The latest time that a device must actually be suspended, drawing no more than the suspend current from the bus. SMSC USB3280 DESCRIPTION 0 (reference) HS Reset T0 + 3. 0ms < T1 < HS Reset T0 + 3.125ms T1 + 100 µs <... -
Page 32: Hs Detection Handshake
SIE requires a stable CLKOUT signal to perform accurate timing. In case 2 and 3 above, CLKOUT has been running and is stable, however in case 1 the USB3280 is reset from a suspend state, and the internal oscillator and clocks of the transceiver are assumed to be powered down. -
Page 33: Figure 8.3 Hs Detection Handshake Timing Behavior (Fs Mode)
Notes: T0 may occur to 4ms after HS Reset T0. The SIE must assert the Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration. SMSC USB3280 DESCRIPTION 0 (reference) T0 < T1 < HS Reset T0 + 6.0ms T1 + 1.0 ms <... -
Page 34: Hs Detection Handshake - Hs Downstream Facing Port
Hi-Speed USB Device PHY with UTMI Interface K State Detect K? INC Chirp Count Chirp Count != 6 & !SE0 J State Detect J? INC Chirp Count Chirp Count != 6 & !SE0 DATASHEET Datasheet Chirp Invalid Chirp Count Chirp Valid SMSC USB3280... -
Page 35: Figure 8.5 Hs Detection Handshake Timing Behavior (Hs Mode)
The earliest time at which host port may end reset. The latest time, at which the device may remove the DP pull-up and assert the HS terminations, reverts to HS default state. SMSC USB3280 Table 8.7 Reset Timing Values DESCRIPTION 0 (reference) T0 <... -
Page 36: Hs Detection Handshake - Suspend Timing
"HS Detection Handshake – HS Downstream Facing Port" Handshake. Revision 1.5 (11-15-07) Hi-Speed USB Device PHY with UTMI Interface Figure 8.6 shows how CLKOUT is used to control the duration of the for completion of the High Speed DATASHEET Datasheet Section 8.9, SMSC USB3280... -
Page 37: Figure 8.6 Hs Detection Handshake Timing Behavior From Suspend
Device removes Chirp K from the bus. (1 ms minimum width) and begins looking for host chirps. CLK "Nominal" (CLKOUT is frequency accurate to ±500 ppm, duty cycle accurate to 50±5). SMSC USB3280 CLK power up time Device Chirp K DESCRIPTION... -
Page 38: Assertion Of Resume
Hi-Speed USB Device PHY with UTMI Interface DESCRIPTION 0 (reference) T0 < T1 < T0 + 10ms. T1 + 1.0ms < T2 < T1 + 15ms T1 + 20ms T3 + 1.33µs {2 Low-speed bit times} DATASHEET Datasheet VALUE SMSC USB3280... -
Page 39: Detection Of Resume
HS Device Attach Figure 8.8 demonstrates the timing of the USB3280 control signals during a device attach event. When a HS device is attached to an upstream port, power is asserted to the device and the device sets XCVRSELECT and TERMSELECT to FS mode (time T1). -
Page 40: Figure 8.8 Device Attach Behavior
Debounce interval. The device now enters the HS Detection Handshake protocol. (HS Reset T0) Revision 1.5 (11-15-07) Hi-Speed USB Device PHY with UTMI Interface Figure 8.8 Device Attach Behavior DESCRIPTION DATASHEET Datasheet VALUE 0 (reference) T0 + 100ms < T1 T1 + 100ms < T2 SMSC USB3280... -
Page 41: Application Diagram
Application Diagram 24 MHz Crystal 4.7uF Ceramic 4.7uF Ceramic 4.7uF Ceramic 0.1uF and/or 0.01uF ceramic capacitors are also required on power supply pins. Figure 8.9 USB3280 Application Diagram SMSC USB3280 UTMI TXREADY RXACTIVE RXERROR DATA 0 DATA 1 DATA 2 XCVRSELECT... -
Page 42: Chapter 9 Package Outline
3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE AREA INDICATED. 4. COPLANARITY ZONE APPLIES TO EXPOSED PAD AND TERMINALS. Figure 9.1 USB3280-AEZG 36-Pin QFN Package Outline and Parameters, 6 x 6 x 0.90 mm Body (Lead-Free RoHS Compliant) TERMINAL #1... -
Page 43: Figure 9.2 Qfn, 6X6 Tape & Reel
Hi-Speed USB Device PHY with UTMI Interface Datasheet Figure 9.2 QFN, 6x6 Tape & Reel SMSC USB3280 Revision 1.5 (11-15-07) DATASHEET... -
Page 44: Figure 9.3 Reel Dimensions
Hi-Speed USB Device PHY with UTMI Interface Datasheet Figure 9.3 Reel Dimensions Note: Standard reel size is 3000 pieces per reel. Revision 1.5 (11-15-07) SMSC USB3280 DATASHEET...
Need help?
Do you have a question about the USB3280 and is the answer not in the manual?
Questions and answers