Table of Contents
Advertisement
Quick Links
Download this manual
See also:
User Manual
Arria 10 UHD Scaler and Mixer Design Example
User Guide
Date: 8/24/16
Revision: 1.0
©2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS
and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in
other countries. All other words and logos identified as trademarks or service marks are the property of their respective hol ders as
described at www.altera.com/common/legal.html. Al tera warrants performance of its semiconductor products to current
specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and serv ices at
any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product,
or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the la test
version of device specifications before relying on any published information and before placing orders for products or services.
Advertisement
Table of Contents
Related Manuals for Altera Arria 10
Summary of Contents for Altera Arria 10
- Page 1 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the la test...
-
Page 2: Table Of Contents
Table of Contents Introduction..........................3 Theory of Operation ........................3 Overview ..........................3 Clocking Scheme ........................3 DisplayPort IP Core ......................... 6 Video and Image Processing..................... 7 External Memory Interface .....................12 NIOS II Processor........................13 Push Button..........................13 LED .............................13 Files and Folders Structure ......................14 Quick Start Guide........................16 Hardware Requirements ......................16 Related links: ........................16... -
Page 3: Introduction
IP core with a video processing pipeline based on IP cores from the Altera Video and Image Processing suite. The design delivers high quality up, down scaling and video mixing. The reference design targets Arria 10 devices and use the latest 4K ready IP cores from the Video and Image Processing Suite. -
Page 4: Clocking Scheme
JTAG to Avalon-MM master bridge 2) PHY subsystem a. Simplex TX and RX Native PHY b. TX fPLL c. Altera PHY reset controller d. Bitec dynamic reconfiguration module e. Reconfiguration arbiter 3) Clock subsystem a. IO PLL for video data path Figure 1 shows the detailed block diagram for VIP. - Page 5 development kit Bitec dynamic reconfiguration controller Transceiver reconfiguration arbiter Altera PHY reset controller TX PLL and TX/RX transceiver channel reconfiguration interfaces NIOS II CPU and peripherals Video PLL input reference clock dp_refclk External 135MHz...
-
Page 6: Displayport Ip Core
The 160MHz clock output from the video PLL drives the DP sink and CVI interface. This interface runs at input video pixel clock domain; this clock frequency must be equal or greater than the required pixel clock frequency of the input video stream. According to the ANSI/CEA-861-F standard, the 3840 x 2160 @ 60Hz video stream requires 594.0 MHz pixel clock. -
Page 7: Video And Image Processing
With 4 lanes @ 5.4Gbps, the aggregated bandwidth of 21.6Gbps is sufficient to support the 4K video stream at 60Hz refresh rate. Symbol output mode Dual Symbol mode affects the transceiver parallel bus (source) width and the DP IP core clock frequency. DP IP core Symbol input mode (sink) is synchronized with the transceiver parallel clock output whose frequency is link rate / transceiver... - Page 8 Here are the brief descriptions of each VIP suite IP core used in this design: Clocked Video Input II The clocked video input II converts DP sink video output format to Altera proprietary Avalon-ST video signal format. This signal format strips all horizontal and vertical blanking information from the video leaving only active picture data.
- Page 9 The frame buffer uses the DDR3 memory to perform triple buffering that allows the video and image processing pipeline to perform frame rate conversion between the incoming and outgoing frame rates. The output frame rate is fixed at 60 fps, but the design can use any input frame rate up to 60 fps.
- Page 10 Bits per pixel per color plane Number of Color planes Number of pixels transmitted in 1 clock cycle Stream Cleaner Maximum frame width 3840 Maximum frame height 2160 Enable control slave port Discard all user How user packets are handled packets received Maximum input frame width 3840...
- Page 11 Add extra pipelining registers Reduced control slave register readback No user packets How user packets are handled allowed Maximum frame width 3840 Maximum frame height 2160 Number of color planes Bits per pixel per color plane Pixels in parallel Avalon-MM master (s) local Frame Buffer II ports width AV-MM burst target write...
-
Page 12: External Memory Interface
TX video data rate. It writes to memory to store input pixels and reads from the memory to retrieve video frames and output them. The Arria 10 FPGA Development Kit has a HiLo connector for the DDR3 module. The DDR3 module is part of the development kit accessories. The module has x72 @ 1067MHz interface. -
Page 13: Nios Ii Processor
Change the display mode Mode (Pass-through, Downscale or Upscale) Table 5: Push button usage The following table lists the green LEDs used in the design and the corresponding reference designators on the Arria 10 FPGA Development Kit. Function Schematic net Reference Description Number/IO... -
Page 14: Files And Folders Structure
DP sink C18/1.8V USER_LED_G6 2-bit indicator of the link link rate D18/1.8V USER_LED_G7 rate at DP sink; LED arrangement is {D3, D4}: 00 = 1.62 Gbps (RBR) 01 = 2.70 Gbps (HBR) 10 = 5.40 Gbps (HBR2) If LED D3 is lighted while LED D4 is off, the DP sink is operating at HBR2 link rate Table 6: LED status indictor... - Page 15 is executed. top.qpf and top.qsf The Quartus Prime project and setting files for this reference design. control.qsys and vip.qsys Control.qsys file belongs to the top level QSYS system while vip.sys file belongs to the VIP QSYS subsystem. Do not include the vip.qsys file in top.qsf file to avoid synthesis error.
-
Page 16: Quick Start Guide
Quick Start Guide Hardware Requirements The following hardware is required to run this reference design: Arria 10 GX FPGA Development Kit (FPGA part number: 10AX115S3F45E2SGE3) DDR3 HiLo module installed on the development kit Bitec FMC daughter card ... -
Page 17: Viewing The Results
1080p and then upscale to 4K in upscale mode as shown in figure 6, no changes in Pass-through mode. Note: If you do not see visible output on the monitor, press push button PB0 (S3) to generate a reset, causing the DisplayPort TX core to re-train the link. Figure 3: Arria 10 FPGA Development Kit hardware setup... - Page 18 Figure 4: Image from PC mixed with color bar background and OSD ICON Figure 5: Upscale to 4K from 1080p...
-
Page 19: Re-Build The Nios Ii Software
Figure 6: Clipped and Upscale to 4K Figure 7: Display mode, Input and Output resolution on Nios II terminal Re-build the NIOS II Software If you change the NIOS II SW, you can re-build the NIOS II SW using the NIOS II command shell by typing ./build_sw_vip.sh or ./build_sw_dp.sh at the reference design project folder. -
Page 20: Know Issue
260 GPU and DELL P2415Q 4K monitor. Please adjust the resolution and refresh rate to match the capability of your monitor. Reference DisplayPort IP Core User Guide https://www.altera.com/en_US/pdfs/literature/ug/ug_displayport.pdf Video and Image Processing Suite User Guide https://www.altera.com/en_US/pdfs/literature/ug/ug_vip.pdf VESA DisplayPort Standard, Version 1, Revision 2a, May 23, 2012 ...