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Remote Start/Stop
As shown in the Backplane Wiring Plan (Appendix D),
the control panel switch contact points are brought
out to the backplane (slot 16) to facilitate hardware
testing or the addition of remote control.
For ex-
ample, one may incorporate remote control through
appropriate use of the signals XCLR-N(16-l4) and
DMA¢UT-N(16-7).
The signal XCLR-N has the same effect
as RESET.
It must have sufficient duration to reset
COS/MaS latches.
After XCLR, the occurrence of a
single DMAOUT-N will start the machine as though one
had depressed RUN PROGRAM, i.e., at memory location
0001.
This external DMAOUT should be no wider than
one machine cycle (turn it off with TPA).
Bus Deseparator (GBA)
Some users may want to experiment with use of the two-
way
COS~~C
data bus.
For them the inclusion of Bus
Separators in the Microkit is an inconvenience.
An
optional module, GBA, will undo the bus separation
when placed in either slot 13 (memory side) or slot 18
(I/O side).
(The module logic shown in the Appendix
includes signal names valid for slot 18.)
Microkit Dynamic Characteristics
COS~~C
CPU timing and dynamic specifications are to be
foun4 in the COSMAC Microprocessor Manual and in the
COS}4AC Data Sheet.
COSMAC based products should be
designed to those specs.
The Microklt lnterface is
designed to facilitate functional experiments.
The
interface supply voltage, VDD, of +S volts and the
modular construction, and consequent capacitive loading,
make it a slower system than that which
can be supported
by the
COS~~C
CPU chip set.
The shortest duration signals in the Microkit are TPB-Nl
and the strobed I/O signals dervied from TPB.
(SI¢O-P
to SI¢7-P).
These timing signals occur late in a
machine cycle to indicate that the data present on the
bus (from a memory access) is valid.
Since these signals
are relatively short, it is prudent to use them only for
strobing data.
The earlier timing pulse, TPA-Nl, is
considerably wider and should be used where a general
purpose strobe is required.
Memory timing requirements for user added memory have
been given earlier in the "Memory Module Addressing
Details" section.
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