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Lnterrupt; Chapter 3 Register Details And Use; Intm - Siemens 6ES5-424 Technical Reference Manual

Counter module.
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Chapter 3
Register Details And Use
The counter module's operation is totally software driven.
Complete manipulation of the five counters is accomplished
by writing software which set various registers with values
predefined in the module's firmware. In this section, detailed
information is presented on the registers and the selections
available. The registers and their abbreviations are:
lnterrupt Mask Register
-
INTM
lnterrupt lnformation Register
-
INTl
Master Mode Register
-
MM
Counter Mode Register
-
CM
Control Register
-
CTRL
Function Number Register
-
FNR
Error Signal Register
-
FEM
Result of Counter 1
-
E l
Result of Counter 2
-
E2
Result of Counter 3
-
E3
Result of Counter 4
-
E4
Result of Counter 5
-
E5
Load Register
-
L
Hold Register
-
H
Alarm Register
-
A
3.1 INTM
-
lnterrupt Mask Register
The interrupt mask register allows you to enable or disable
the group interrupt (set via switch S2) and the system interrupts
(set via switch S3) for each of the interrupts available.
To enable an interrupt, write a logic 1 in the corresponding
bit of the INTM register. The AM 9519 interrupt controller chip
is an edge sensitive device and will generate a group and a
system interrupt when a transition of the enabled interrupt
input is detected.
lnterrupt processing requires a properly defined organizational
block for the type of PC used to handle these interrupts.
This includes the use of a reset call using the standard
function block which will be described in detail in Chapter 4
of this manual. The setting of switches S2 and S3 was
described in Section 2.2 and 2.3.
a
INTM
-
Low Order Byte
Subaddress xxx5, Write
Bit
7
6
5
4
3
2
1
0
Z1
22
23
24
25
T1
T2
T3
'
I
Counter OUT signals
Gate signals
Z1
-
25
=
The counter OUT signal from the AM 9513. These
signals must have the CM register set to active
high or active low.
T1
-
T3 = The gate input signals for gates 1
-
3. The inputs
may be manipulated by the setting of the S4
switch. See Section 2.4.
INTM
-
High Order Byte
Subaddress xxx4, Write
Bit
15
14
13
12
11
10
.
9
8
R
E
O
O
O
O
O
O
T
not used
Error Signal
P
Ready Signal
1 = interrupt enabled
2 = interrupt disabled
When the error signal enable bit of the INTM is set to a logic 1,
a group interrupt will occur when an error occurs in the FEM
register. You must check the I N 1 register to identify the
interrupt within the INTM register, and then check the FEM
register to identify the initial cause of the interrupt.
When the ready signal enable bit of the INTM is set to a logic 1,
a group interrupt will occur when the 6ES5 242's internal
8085 microprocessor has completed its internal program
processing and is available to be accessed.
NOTE:
The INTM register is used only to enable the group and
system interrupts for the module. If an interrupt occurs it will
appear in the INTl register, regardless of the setting in the
INTM register.
Refer to Chapter 4 for setting the INTM register with standard
software blocks. The INTM register can be set using the PA
mode of FB 159. Care must be taken when using the PA
mode because the INTM register is set each time the PA mode
is used for a particular counter.
3.2 INTl
-
lnterrupt lnformation Register
The interrupt information register is used to store any interrupts
that may occur on the module. The bit assignments of the INTI
register are the same as the INTM register. An interrupt is
identified by a logic 1.
When an interrupt occurs, you must read the value of the INTl
register to identify which interrupt has occurred. The INTl
register may be read directly using a "L PWxx" instruction or
by checking the value of the data word assigned to represent
the INTl register within the data block (defined when using
the standard software). This programming is described in more
detail in Chapter 4 of this manual.
INTM
-
Low Order Byte
Subaddres xxxl , Read
Bit
7
.
6
5
4
3
2
1
0
Z1
22
23
24
25
T1
T2
T3
'
I
Counter OUT signals
Gate signals
Z1
-
25
=
The counter OUT signal,from the AM 9513.
T1
-
T3
=
The gate input signals for gates 1
-
3.
INTM
-
Hig Order Byte
Subaddress xxx0, Read
Bit
15
14
13
12
11
10
9
8
R
E
O
O
O
O
O
O
T
not used
Error Signal
Ready Signal
NOTE:
The INTl register will provide an indication of an interrupt
whenever an interrupt occurs, regardless of the INTM regis-
ter's settings.

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