Kenwood NX-420 K Service Manual page 15

When the frequency is controlled by the PLL, the frequen-
cy convergence time increases as the frequency difference
increases when the set frequency is changed. To supple-
ment this, the ASIC is used before control by the PLL IC
to bring the VCO oscillation frequency close to the desired
frequency. As a result, the VCO CV voltage does not change
and is always stable at approximately 2.5V.
The desired frequency is set for the PLL IC by the ASIC
(IC607) through the 3-line "SDO1", "PCK_RF", "/PCS_RF"
serial bus. Whether the PLL IC is locked or not is monitored
by the ASIC through the "PLD" signal line. If the VCO is not
the desired frequency (unlock), the "PLD" logic is low.
"PLLMOD" receives the modulation data from the DSP
(IC601).
Q403
50C
BUF
IC402
CV
ASIC
SD01,/PCS_RF
PCK_RF,PLD
IC601
DSP
PLL MOD
6. Control Circuit
The control circuit consists of CPU in ASIC (IC607) and
its peripheral circuits. CPU mainly performs the following;
1) Switching between transmission and reception by PTT
signal input.
2) Reading system, zone, frequency, and program data from
the memory circuit.
3) Sending frequency program data to the PLL.
4) Controlling squelch on/off by the DC voltage from the
squelch circuit.
5) Controlling the audio mute circuit by decode data input.
6-1. ASIC
The ASIC (IC607) is a 32-bit RISC processor, equipped
with peripheral function and ADC/DAC.
This ASIC operates at 18.432MHz clock and 3.3V/1.5V
DC. It controls the fl ash memory, SRAM, DSP, the receive
circuit, the transmitter circuit, the control circuit, and the dis-
play circuit and transfers data to or from an external device.
CIRCUIT DESCRIPTION
Q404
Q406
Ripple
filter
/T_R
IC401
Q401,Q402
BUF
VCO 1
VCO 2
PLL IC
X400
TCXO
Fig. 6 PLL block diagram
5-4. Local Switch (D411, D412)
The connection destination of the signal output from the
buffer amplifier (Q408) is changed with the diode switch
(D412) that is controlled by the transmission power supply,
50T, and the diode switch (D411) that is controlled by the
receive power supply, 50R. If the 50T logic is high, it is con-
nected to a send-side RF amplifi er (Q101). If the 50T logic is
low, it is connected to a receive-side mixer (IC200).
Q405 Q407
X2 BUF
VCO_MOD
IC607
IC6
BUF
ASIC
6-2. Memory Circuit
The memory circuit consists of the ASIC (IC607), the
SRAM (IC603), and the flash memory (IC600). The flash
memory has a capacity of 32M-bit that contains the trans-
ceiver control program for the ASIC and stores the data. It
also stores the data for transceiver channels and operating
parameters that are written by the FPU. This program can
be easily written from external devices. The SRAM has a ca-
pacity of 1M-bit that contains work area and data area.
Flash memory
Note :
• The fl ash memory stores the data that is written by the
FPU (KPG-141D), tuning data (Deviation, Squelch, etc.)
,and firmware program (User mode, Test mode, Tuning
mode, etc.). This data must be rewritten when replacing
the fl ash memory.
SRAM (Static memory)
Note :
• The SRAM has temporary data area and work area.
NX-420
D411,D412
Q408
TX/RX
BUF
SW
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