Camera Signal Process Block Diagram - Sony DCM-M1 Service Manual

DCM-M1

3-2. CAMERA SIGNAL PROCESS BLOCK DIAGRAM

VC-216 BOARD (1/2)
(SEE PAGE 4-13, 17)
CCD IMAGER
IC001
BUFFER
CCD OUT 8
Q001
TIMING GENERATOR
IC101
7 Vp-p
H
REC/PB
CLPDM
V1 4 26 V1
V2 3 25
V2
V3 2 28 V3
V4 1 31 V4
SUB
13 33 VSHT
VCK (CL)
7 Vp-p
H
REC/PB
3.28 Vp-p
18 MHz
REC/PB
RG 10 RG
18
H1 11 21 H1
H2 12 22 H2
3.12 Vp-p
DSGAT
16.33 MHz
REC/PB
35 37 38 39 40
TO CAMERA CONTROL
1
(SEE PAGE 3-6)
05
1 Vp-p
H
CDS, AGC, A/D CONVERTER
REC/PB
IC102
26
CDS
27
PBLK
PBLK 2 19
CLPDM
1 23
TIMING
21 22 16
XSHP 15
XSHD 16
12
ZSG1
ZSG1 34
3.84 Vp-p
VGAT
VGAT 36
18 MHz
ZV1
ZV1 41
REC/PB
ID
ID 48
TGHD
AHD 44
TGVD
AVD 45
CK 7
2.88 Vp-p
V H
OSCO 5
X101 REC/PB REC/PB
36MHz
OSC ADJ
OSCI 4
IC104
42
2.24 Vp-p
36 MHz
REC/PB
3-3
CLPOB 20
78
D0
I
2 89
D9
A/D
AGC S/H I I
CONVERTER
11 80
PGA CONT 1
29 3
PGA CONT 2
30 2
18 40
18MHz
69
73
74
71
75
72
76
77
3.04 Vp-p
6
CAMERA Y/C PROCESS
IC105 (1/2)
50
CLPOB
I
47
YO 0
I
YO 7 45
I
42
AD 0
I
AD 9
CO 0 40
I I
CO 3 37
CAMERA
HDO 51
Y/C
AGC CONT 2
PROCESS
VDO 52
AGC CONT 1
FLDO 53
CHCK
MCKO 63
VCK 65
PBLK
ZSG1
VGAT
ZV1
ID
TGHD
Approx.
TGVD
3.4 Vp-p
13.5 MHz
REC/PB
FRQ
SIGNAL PATH
VIDEO SIGNAL
CHROMA Y Y/CHROMA
REC
3-4
A
CN101 (1/2) TO A/V DATA CONTROL,
VIDEO OUT
8
Y0-Y7 (SEE PAGE 3-7)
I
15
3.04 Vp-p
H
REC/PB
16
C0-C3
I
19
CAM HD
7
CAM VD
6
2.88 Vp-p
V
REC/PB
13.5MHz
SPCKO
3
2.96 Vp-p
2V
REC/PB
CAM DD ON
B
TO SYSTEM CONTROL
29
(SEE PAGE 3-15)
2
TO CAMERA
CONTROL
(SEE PAGE 3-6)