A/V Data Control, Video Out Block Diagram - Sony DCM-M1 Service Manual

DCM-M1

3-4. A/V DATA CONTROL, VIDEO OUT BLOCK DIAGRAM

MAIN BOARD (1/7)
(SEE PAGE 4-29, 48, 53, 59)
CN8101 (1/3)
8
Y0 – Y7
A
ı
15
TO CAMERA SIGNAL
PROCESS
C0 – C3
16
(SEE PAGE 3-4)
ı
19
CAM_VD
6
CAM_HD
7
SPCKO
3
V
REC/PB
TO AUDIO 3
(SEE PAGE 3-18)
DATA BUS
ADDRESS BUS
64M
EDO DRAM
IC8102
2 – 5 7 – 10 2 – 5 7 – 10
• • • •
19 – 24 27 – 32
•
41 – 44 46 – 49 41 – 44 46 – 49
• •
37 38 13 14 37 38
TO MD SERVO
4
(SEE PAGE 3-14)
TO MD SIGNAL
PROCESS 5
(SEE PAGE 3-12)
TO MD SIGNAL
6
PROCESS
(SEE PAGE 3-12)
D-FF
IC8104 (1/2)
MBCK
2
1D X1Q
X1CK 3
05
AUDIO & VIDEO DATA CONTROL
IC8101
92
ADC0/YIN0
ı
ı IO0 71
98
• ADC7/YIN7
100
C0/CIM0
89
•
91 ID/CIN1
•
101 ADC8/CIN2
•
109 ADC9/CIN3
111 EXVD
110 EXHD
112
VCLK
3.04 Vp-p
IO1 72
H
2.88 Vp-p
REC/PB
188 ACLK
ACLK
195
RCK4
SYS_ACDO
194
ACDO
700 mVp-p
SYS_ACDI
192
ACDI
XABS
H
190
XABS IO3 84
REC/PB
XARQ
191
XARQ
IO2 83
136 – 140
360 mVp-p
•
142 – 147
•
149 – 153
H
DRAMD0 VHD 66
•
155 – 158 REC/PB
ı
•
160 – 163 DRAMD31
•
165 – 169
•
171 – 173
VVD 67
3.6 Vp-p
174 – 176
DRAMA0
H
•
178 – 184
ı
REC/PB
•
186 187 DRAMA11
•
64M
EDO DRAM
IC8103
3.1 Vp-p
19 – 24 27 – 32
•
V
37
REC/PB
ı
MEC0
41
ı
•
43
MEC7
ı
45
54
13 14 MVP0
•
52
ı
ı
MVP7
46
130 RAS
129 DWE BITO 32
135 CAS0 BITI 33
134 CAS1 HANDO 34
132 CAS2 HANDI 36
131 CAS3
FSY 210
SCLK_SYS
196
SCLK
SO
197
SO
SI
2 – 4
198
SI
•
224 – 227
DDO
205 DDO •
229 – 233
DDI DATA0
•
206 DDI ı
235 – 240
DSYNC
DATA31 •
207 242 – 248
DSYNC
DCLK •
250 – 256
209
DCLK
512FS
189
RCLK
MDTI
200 MDTI
5 – 8
MLRCK
202 MLRCK •
10 – 15
ADDR1
•
ı 17 – 23
•
ADDR23
25 – 29
•
31
6 203 MBCK
128 PLL OUT XRD 213
XWE3 214
XWE2 215
212
MCLK XWE1 217
XWE0 218
XWAIT 219
XINT 220
XCS 222
3.52 Vp-p
27 MHz
REC/PB
TRST 123
RST 211
3-7
Y VIDEO SIGNAL AMP
IC4004
FL4002
IN OUT
BUFFER
LPF 4 2
Q4002
STBY
1
1.12 Vp-p
C VIDEO SIGNAL AMP
H
IC4002
REC/PB 1
STBY
FL4001
IN OUT
BUFFER
BPF 4 2
Q4001
BUFFER
Q4005
BUFFER
Q4006
BUFFER
Q4007
IC4006
1 7
IC4006
6 3
1 7 IC4009
IC4009
6 3
MEC0 – MEC7 C_OUT_OFF
S_OUT_OFF
S_JACK_DET
4_JACK_DET
SYS_MVP0 – SYS_MVP7
SYS_BITO
SYS_BITI
HANDO
HANDI
FSY_INT
MCLK_BUFF
D0 – D31
TO SYSTEM CONTROL
8
(SEE PAGE 3-16)
A0 – A23
FSY_INT
RD
DQMUU_ICIOWR
DQMUL_ICIORD
DQMLU_WE1
DQMLL_WE0
SYS_WAIT
SYSCHIP_INT
D-FF
IC8020 (1/2)
CPU_CS4_100
5 1Q 1D 2
3 X1CK
SIGNAL PATH
D-FF
IC8104 (2/2)
DEV_RESET
9 2Q 2D 12
REC
11 X2CK
Approx.
3.4 Vp-p
13.5 MHz
REC/PB
Y VIDEO SIGNAL AMP
IC4003
CN3002
(1/4)
IN OUT
2
4 6
•
3
SAG
STBY
2.32 Vp-p
1
H
REC/PB
4
C VIDEO SIGNAL AMP
IC4001
1
STBY
IN OUT
4 2 3
COMPOSITE VIDEO
SIGNAL AMP
IC4005
Y IN
2
OUT1, 2
6
• 10
7
4
12
C IN
VCC
8
SWITCH
1.48 Vp-p
Q4002, 4004 CN4313
H
(1/3)
REC/PB
12
11
10
3
4
CN4511
(1/2)
25
24
26
27
23
7 TO MPEG ENCODE
(SEE PAGE 3-9)
MD SIGNAL VIDEO SIGNAL
AUDIO
SIGNAL
MD1 MD2 CHROMA Y Y/CHROMA
PB
3-8
JACK BOARD (1/4)
(SEE PAGE 4-119)
CN3003
(1/4)
S
S_Y
G
6 Y J4001
S. VIDEO
C
G
S
S_JACK_DET
4
S_C
3
LINE OUT L
VIDEO OUT
J3003 (1/2)
10
4_JACK_DET
12 AUDIO/VIDEO
LINE OUT R
PANEL_Y
PANEL_R-Y
PANEL_B-Y
LCD_XHD
LCD_XVD
E TO LCD
(SEE PAGE 3-19)
EVF_Y
EVF_R-Y
EVF_B-Y
EVF_XHD
EVF_XVD
F TO EVF
(SEE PAGE 3-21)