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Data Interfaces
A.8.6
Connector Pinout Data
A.8.6.1
ASI Connector Pinout
The ASI interface is shown below:
A.8.6.2
LVDS Connector Pinout (J6)
The LVDS connector (Table A-41) is a 25-Pin D female type, with threaded jack nuts.
LVDS signal levels are as defined in EN 50083-9. The differential sense of all signal
pairs is a logic "1" when "A" is positive with respect to "B." Some DBS applications
require an inverted data or clock polarity and control of the signal polarity (normal or
inverted) is provided.
Input / Output (I/O) of the interface is determined by a) whether it is plugged into a
modulator or demodulator and b) Loopback or Loop Thru programming.
Clock A
System Gnd / REFCLKB
Data 7 A(MSB/Serial)
Data 6 A
Data 5 A
Data 4 A
Data 3 A
Data 2 A
Data 1 A
Data 0 A
DVALID A
SYNC A
Cable Shield
Clock B
System Gnd / REFCLKA
Data 7 B (MSB/Serial)
Data 6 B
Data 5 B
Data 4 B
A–72
J3, J4
Transmit Data Input, BNC female
J7
Receive Data Output, BNC female
Table A-41. LVDS Connector Pinout (J6)
Signal Function/Name
Pin #
Type
1
I / O
Mod / Demod
2
O / Gnd
Mod / Demod,
Demod – GND only, no clock
available
3
I / O
Mod / Demod
4
I / O
Mod / Demod
5
I / O
Mod / Demod
6
I / O
Mod / Demod
7
I / O
Mod / Demod
8
I / O
Mod / Demod
9
I / O
Mod / Demod
10
I / O
Mod / Demod
11
I / O
Mod / Demod
12
I / O
Mod / Demod
13
I / O
Mod / Demod
14
I / O
Mod / Demod
15
O / Gnd
Mod / Demod
Demod – GND 0nly, no clock
available
16
I / O
Mod / Demod
17
I / O
Mod / Demod
18
I / O
Mod / Demod
19
I / O
Mod / Demod
SDM-2020 Satellite Demodulator
Comment
Rev.3
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