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Car Audio DSP
Car Audio DSP
Car Audio DSP
LC750100W
LC75010W
LC75010W
Overview
The LC75010W is a 1-chip DSP that is ideal for car stereos as it incorporates major required functions
such as A/D, D/A, and a DSP core. This is a custom IC that incorporates DSP software based on the user
specifications.
Features
Analog source selector
Single input: 3 systems, differential input: 1 system
A/D
Stereo: 1 system
DSP core
24-bit fixed decimal point DSP
D/A
4 systems
Analog volume
4 systems
Microcontroller interface
1 system (SANYO Electric original format)
(CCB: Computer Control Bus)
Block Diagram
Als3
DSP · CORE
Als4
(24bit)
AINLP1
AINLN1
ADC
AINRP1
(20bit)
AINRN1
AINLP2
AINRP2
Program ROM
AINLP3
ADC
(8kw)
AINRR3
(20bit)
AINLP4
AINRP4
Ars3
Ars4
Data RAM
(896w)
PLL
VCO
VCO
13 Car Audio
W
Analog characteristic (S/N)
Typ. 90 dB (Note)
Analog characteristic (dynamic range)
Typ. 90 dB (Note)
Analog characteristic (THD + N)
Typ. -85 dB (Note)
Power supply voltage (5 V)
4.75 V to 5.25 V
Power supply voltage (3.3 V)
3.0 V to 3.6 V
Operating ambient temperature
-40°C to 85°C
Package: SQFP100 (14
14)
Note: Analog characteristics are according to SANYO Electric measurement conditions.
CCB is a SANYO's original bus format and all the
bus addresses are controlled by SANYO.
VFLO
C
1µ
R
VFLI
DAC
L.P.F
(24bit)
AOUT1
VFRO
Vref
C
1µ
R
VFRI
DAC
L.P.F
(24bit)
AOUT2
VRLO
Vref
C
1µ
R
VRLI
DAC
L.P.F
(24bit)
AOUT3
VRRO
Vref
C
1µ
R
VRRI
DAC
L.P.F
(24bit)
AOUT4
Vref
DVDD
3.3V
DVSS
AVDD
5V
AVSS
CCB
VREF
Dolby Headphone IC
LC83200W
LC83200W
LC83200W
Overview
The LC83200W is an IC that integrates the functions required for Dolby Headphone on one chip. It
generates a Dolby Headphone audio output signal from either a 5.1-channel or 2-channel audio input.
The LC83200W provides DH1, DH2, DH3, and Stereo Mixdown as room modes and can be used in all
products that have a headphone pin.
Features
Supports Dolby Headphone room modes DH1, DH2, DH3, and Stereo Mixdown.
Sampling rate of 44.1/48 kHz
Audio serial input: 2 channels (L, R) or 5.1 channels (L, C, R, Ls, Rs, LFE)
Audio serial output: 2 channels (L, R)
External memory not required
50 MHz internal operation frequency (External clock: 27 MHz/13.5 MHz or 512/256 fs clock)
2 power supplies (Logic block: 2.5 V; I/O block: 3.3 V)
PLL stop (PLL STOP pin)
Registers can be controlled through serial setting via microcontroller I/F or parallel setting via pins.
Package: SQFP48 (7
7)
Manufactured under license from Dolby Laboratories.
"Dolby" and the double-D symbol are trademarks of Dolby Laboratories.
Confidential unpublished works. Copyright 1998–1999 Dolby Laboratories.
All rights reserved.
Block Diagram
3
R
MCLOCK
SYS CLK
VCNT
PLL
Data I/O I/F
PDO
Output registers
L
R
ENABLE
FIR Filter
CLOCK
Core
DATA
(DSP)
R
R
RESET
RESET
PLL
PLL STOP
STOP
Input registers
L
R
Ls
Rs
C
LFE
Data
RAM
11.5k X 24bits
Program
ROM
15k X 32bits
14 Car Audio
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