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RDS Demodulator ICs
RDS Demodulator ICs
LC72723/M
LC72723/M
Overview
The LC72723 and LC72723M are Radio Data System (RDS) demodulation and signal-processing ICs.
These ICs integrate a bandpass filter, the demodulation circuit, and data buffer RAM on the same chip and allow
the RDS data to be read out in slave mode operation with an externally provided clock input signal.
(Master mode operation, in which the data is output in synchronization with the internal RDS clock output, is also
supported.)
Functions
Bandpass filter: switched capacitor filter (SCF)
RDS demodulation: 57 kHz carrier regeneration, clock regeneration, biphase and differential decoding
Buffer RAM: 128 bits (about 100 ms)
Data I/O: Data readout in either master or slave mode
RDS ID detection: Supports ID reset
Standby mode: The crystal oscillator is stopped
Fully adjustment free
Packages:(LC72723) : DIP16(300mil)
(LC72723M) : MFP16(225mil)
Block Diagram
V REF
+5V
FLOUT
Vdda
REFERENCE
VOLTAGE
Vssa
57kHz
BPF
MPXIN
ANTIALIASING
SMOOTHING
(SCF)
FILTER
FILTER
TEST
TEST
71 Car Audio
CIN
CLOCK
+
PLL
RECOVERY
-
(57kHz)
(1187.5Hz)
V REF
DATA
DECODER
RAM
(128 bit)
CLK(4.332MHz)
RDS-ID
DETECT
OSC
X IN
X OUT
Overview
The LC72720Y and LC72720YV are single-chip system ICs that implement the signal processing required by the
European Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System
Committee) RDBS (Radio Broadcast Data System) standard. These ICs include band-pass filter, demodulator,
synchronization, and error correction circuits as well as data buffer RAM on chip and perform effective error
correction using a soft-decision error correction technique.
Functions
Band-pass filter: Switched capacitor filter (SCF)
Demodulatior: RDS data clock regeneration and demodulated data reliability information
Synchronization: Block synchronization detection (with variable backward and forward protection
conditions)
Error correction: Soft-decision/hard-decision error correction
Buffer RAM: Adequate for 24 blocks of data (about 500 ms) and flag memory
Data I/O: CCB interface (power on reset)
Features
Error correction capability improved by soft-decision error correction
The load on the control microprocessor can be reduced by storing decoded data in the on-chip data
buffer RAM
Two synchronization detection circuits provide continuous and stable detection of the synchronization
timing
Data can be read out starting with the backward-protection block data after a synchronization reset
Fully adjustment free
Low voltage (supply voltage: 3.0 V min) type
Operating power-supply voltage: 3.0 to 3.6 V
Operating temperature: -40 to +85 C
Packages: (LC72720Y) : DIP24S(300mil)
Block Diagram
+5V
Vddd
+3.3 V
Vssd
Vdda
RDDA
Vssa
RDCL
MPXIN
MODE
RST
DO
CL
RDS-ID/
DI
READY
CE
T1
T2
T3 to T7
Single-Chip RDS Signal-Processing System IC
Single-Chip RDS Signal-Processing System IC
LC72720Y/YV
(LC72720YV) : SSOP30(275mil)
V REF
FLOUT
CIN
+
REFERENCE
-
(57kHz)
VOLTAGE
V REF
57kHz
BPF
ANTIALIASING
SMOOTHING
(SCF)
FILTER
FILTER
RAM
ERROR CORRECTION
CCB
(24 BLOCK DATA)
(SOFT DECISION)
CLK(4.332MHz)
MEMORY CONTROL
TEST
OSC/DIVIDER
X IN
X OUT
:CCB is SANYO's original bus format.
All bus addresses are managed by
SANYO for this format.
+3.3 V
Vddd
CLOCK
PLL
RECOVERY
(1187.5Hz)
Vssd
DATA
RDS-ID
DECODER
SYNC
SYNC/EC CONTROLLER
SYR
SYNC
SYNC
DETECT-1
DETECT-2
72 Car Audio
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