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4-2.
Clock System
RF
from RF AMP IC501
3
37
pin RF-OUT
Fig. 4-6. shows a block diagram of the clock system.
For the master clock of both system controller (IC801) and DSP/digital servo (IC601), 384 fs (fs = 44.1kHz) available at
X301 connected between Pin 5 [XT1] and Pin 4 [XT0] in the D/A converter (IC301) is supplied from Pin 6 [CLK0].
The timing generator located in the interior of the DSP/digital servo divides a frequency of 384 fs input at Pin $• [X1] so
as to output 48 fs (bit clock) from Pin $¡ [BCK], fs (L/R clock) from Pin #ª [LRCK] and 4 fs from Pin @∞ [CK176].
Based on a frequency of 96 fs from the timing generator, the EFM PLL unit generates a PLL clock (PLCK) so as to
perform EFM demodulation in a subsequent stage of the EFM decoder.
A frequency of 48 fs (bit clock) supplied to Pin !ª [MCK] in the sled motor control (IC803) is used as the master clock for
the controller located inside. And the bit clock (BCK) and L/R clock (LRCK), both output to the D/A converter, are used as
the timing signal for the audio data output from the ATRAC block in the DSP/digital servo. (For details, refer to 7-2. Playback
Operations.)
A frequency of 4 fs, which is output from Pin @∞ [CK176] in the DSP/digital servo to Pin @• [CLK] in the DC-DC converter is
used as a switching signal to drive the STEP-UP circuit in the power supply unit. (For details, refer to 5-1. Outline of Power supply
Circuit Operations.)
IC601
DSP/DIGITAL SERVO
EFM/ACIRC
RAM
DECODER
CONTROLLER
BCK
(48fs)
41
TIMING
(96fs)
EFM
GENERATOR
PLL
LRCK
39
ADC
48
25
(4fs)
28
IC901
DC-DC CONVERTER
Fig. 4-6. Clock System Block Diagram
— 14 —
(48fs)
IC301
D/A CONVERTER
BCK
7
LRCK
(fs)
9
6
5
X301
(384fs)
(384fs)
IC803
SLED MOTOR
MCK
CONTROL
19
IC801
SYSTEM CONTROLLER
20
4
(384fs)
NOTE : fs = 44.1[kHz]
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