Table of Contents
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Outline of Operations
XWK1
XWK2
XWK3
XWK4
FFCLR
XRST
SLEEP
Start operation Input Circuit
FFLCR
XRST
VB2/VB1
Standby Power Supply Generation Circuit
Latch5
Latch1
S
Q
R
S
Q
R
Latch2
S
Q
R
Latch3
S
Q
R
Latch4
S
Q
R
VRMC
M1
VC
M2
VB1
VDD
M3
VSTB
M4
VB2
Wake
The start circuit operates when the wake terminal becomes
HIGH.
Latches at the rising edge of Latch 1 to 4.
Latches when Latch 5 becomes H from L.
Latching is set at the falling edge of XWK1 to XWK4, and
wake is output. At this time, the input terminal which had
become LOW prohibits the latching of other input terminals
from being set until FFCLR becomes HIGH. The FFCLR and
SLEEP terminals are negated while XRST is LOW.
VDD is always output with the highest voltage from amongst
VB1, VB2, and VC.
When XRST is LOW, M1 and M2 go OFF, and when VB2/
VB1 is LOW, M3 becomes OFF, and M4 becomes ON. When
XRST becomes HIGH, M3 and M4 go OFF, and M1 and M2
turn ON.
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