Siemens SIMATIC S7 System Manual page 276

Program instructions
7.6 Counters
HSC status byte
A status byte for each high-speed counter provides status memory bits that indicate the
current counting direction and whether the current value is greater than or equal to the
preset value. The following table defines these status bits for each high-speed counter.
Note
Status bits are valid only while the high-speed counter interrupt routine executes. The
purpose of monitoring the state of the high-speed counter is to enable interrupts for the
events that are of consequence to the operation being performed.
Table 7- 14
HSC0
SM36.5
SM36.6
SM36.7
Reference information
Refer to the following sections for further information:
● High-speed counter instructions (Page 257)
● High-speed counter summary (Page 260)
● Example initialization sequences for high-speed counters (Page 277)
276
Status bits for HSC0, HSC1, HSC2, HSC3, HSC4, and HSC5
HSC1 HSC2 HSC3
SM46.5 SM56.5 SM136.5 SM146.5 SM156.5 Current counting direction status bit:
SM46.6 SM56.6 SM136.6 SM146.6 SM156.6 Current value equals preset value
SM46.7 SM56.7 SM136.7 SM146.7 SM156.7 Current value greater than preset
HSC4 HSC5 Description
0 = Counting down
•
1 = Counting up
•
status bit:
0 = Not equal
•
1 = Equal
•
value status bit:
0 = Less than or equal
•
1 = Greater than
•
System Manual, V2.3, 07/2017, A5E03822230-AF
S7-200 SMART