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C306
C308
C310
C313
C315
C317
100nF
100nF
100nF
100nF
100nF
100nF
VDDMQ
C305
C307
C309
C312
C314
C316
100nF
100nF
100nF
100nF
100nF
100nF
VDDMQ
MD[0..31]
U1A
MD0
73
MD0
MD1
75
MD1
MD2
76
MD2
MD3
78
MD3
MD4
84
MD4
MD5
86
Test pads for DDR
MD5
MD6
88
MD6
MD7
90
MD7
MD8
91
MD8
MCLK0#
MD9
TP25
93
MD9
TP_T_C30
MD10
94
MD10
MCLK0
MD11
TP1
96
MD11
MD12
TP_T_C30
102
MD12
MD13
104
MD13
DQS0
TP2
MD14
106
MD14
MD15
TP_T_C30
108
MD15
MD16
148
MD16
DQM0
MD17
TP3
150
MD17
TP_T_C30
MD18
152
MD18
MD19
154
MD19
MD0
MD20
TP4
160
MD20
MD21
TP_T_C30
162
MD21
MD22
163
MD22
MD23
165
MD23
MD24
TP5
166
MD24
MD25
TP_T_C30
168
MD25
MD26
170
MD26
TP6
MD27
172
MD27
MD28
TP_T_C30
178
MD28
MD29
180
MD29
MD30
181
MD30
MD31
183
MD31
DQM0
79
DQM0
DQM1
97
DQM1
DQM2
159
DQM2
DQM3
177
DQM3
DQM[0..3]
SVP-EX_256
DQS[0..3]
MA[0..11]
C319
C311
100nF
100nF
C318
C320
100nF
100nF
SVP-EX [256]
(1 of 2)
33RX4 TO 100RX4
VDDH3_3
R18
10K
MPUCS0N
R20
10K_DNS
if not a test pad, an enlarged via
- 32 -
underneath the chip or exposed
trace. Possible DQS MCLK
exposed trace, DQ enlarged via
MPUGPIO0
VDDMQ
P_17
GPIO
MPUGPIO1
MPUGPIO2
R3
0R_DNS
MPUGPIO3
R4
0R_DNS
MPUGPIO4
P_17
P_17
17
P_17
18
R8
0R_DNS
FIELD
FLD/IO
SDA_EX
16
SDA
SCL_EX
14
SCL
RP1
203
5
4
100Rx4
AD7
A_D7
AD6
202
6
3
A_D6
AD5
201
7
2
A_D5
AD4
200
8
1
A_D4
197
5
4
AD3
A_D3
AD2
196
6
3
A_D2
AD1
195
7
2
A_D1
AD0
194
8
1
A_D0
RP2
100Rx4
216
RD#
RD_EX
217
33RX4 TO 100RX4
WR
WR#
218
ALE
ALE
219
MPUCS0N
MPUCS0N
220
INT#
INT#
15
V5SF
12
TESTMODE
13
R13
RESET
147
BA1
BA1
145
4K7
BA0
BA0
144
CLKE
CLKE
142
WE#
WE#
MVREF
CAS#
RAS#
TP24
TP_T_C30
CS0#
MCLK0#
MCLK0
MPUGPIO0
A[0..7]
MPUGPIO1
R17
0R
CS
VDDH3_3
R19
10K_DNS
MPUGPIO4
R21
1K
Connector for Amtel AT76C112 Video Output
VDDM
VCC
R1
R2
PWM
1K5
4K7
R5
R7
R6
10R
1
Q1
10K
MMBT3904
10uF/16V
C3
100pF
AD[0..7]
SDA_EX
R9
68R
3V_SDA
SCL_EX
R10
68R
3V_SCL
C4
C5
68pF
68pF
5V-1_CPU
C6
100nF
INPUT
MPUGPIO1
MPUGPIO0
MPUCS0N
0
0
0
0
1
1
1
0
1
1
1
1
VDDH3_3
*CS1N is not a input or output pin
CS1N=0: SVP-EX CPU access enabled
CS1N=1:SVP-EX CPU access disabled
R15
10K_DNS
R16
1K
MPUGPIO0
Qingdao Haier Electronics Co.,Ltd.
Title
SVP-EX 1 of 2
Size
Document Number
B
42PDP TV_MAIN
Date:
Saturday, February 18, 2006
E_PWM
4K7
BRT_CNTL
C1
+
C2
100nF
VD3_3
R12
10K
P_39
For EX52 to use
this table
OUTPUT
*CS1N
MPUGPIO2
MPUGPIO3
1
1
1
0
1
1
1
0
1
1
1
0
RST_SVP
MPUGPIO0
Rev
C-03
Sheet
9
of
30
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