Philips LPC2101 User Manual page 100

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Table 98: UART1 register map
Name Description Bit functions and addresses
U1RBR Receiver Buffer
Register
U1THR Transmit Holding
Register
U1DLL Divisor Latch LSB
U1DLM Divisor Latch MSB
U1IER Interrupt Enable
Register
En.CTS
U1IIR Interrupt ID Reg.
U1FCR FIFO Control
Register
U1LCR Line Control DLAB
Register
U1MCR Modem Ctrl. Reg. CTSen
U1LSR Line Status RX FIFO
Register
U1MSR Modem Status
Register
U1SCR Scratch Pad Reg.
U1ACR Auto-baud Control
Register
U1FDR Fractional Divider
Register
U1TER TX. Enable Reg. TXEN
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
MSB
BIT7 BIT6 BIT5 BIT4
8-bit Read Data
8-bit Write Data
- - -
- -
Int
- - -
FIFOs Enabled -
RX Trigger -
Set Stick Even
Break Parity Par.Selct.
RTSen - LoopBck.
TEMT THRE BI
Error
DCD RI DSR CTS
- - -
- - -
Reserved[31:8]
MulVal
- -
BIT3 BIT2 BIT1
8-bit Data
8-bit Data
- - - En.ABTO En.ABEO R/W
- E.Modem En. RX Enable
St.Int Lin.St. Int THRE Int
- - - ABTO Int ABEO Int RO
- IIR3 IIR2 IIR1
- - TX FIFO RX FIFO
Reset Reset
Parity No. of Word Length Select R/W
Enable Stop Bits
- - RTS
FE PE OE
Delta Trailing Delta
DCD Edge RI DSR
8-bit Data
- - - ABTO
IntClr
- - Aut.Rstrt. Mode
DivAddVal
- - - -
Access Reset Address
[1]
value
LSB
BIT0
RO NA 0xE001 0000
(DLAB=0)
WO NA 0xE001 0000
(DLAB=0)
R/W 0x01 0xE001 0000
(DLAB=1)
R/W 0x00 0xE001 0004
(DLAB=1)
0x00 0xE001 0004
(DLAB=0)
En. RX
Dat.Av.Int
0x01 0xE001 0008
IIR0
FIFO WO 0x00 0xE001 0008
Enable
0x00 0xE001 000C
DTR R/W 0x00 0xE001 0010
DR RO 0x60 0xE001 0014
Delta RO 0x00 0xE001 0018
CTS
R/W 0x00 0xE001 001C
ABEO R/W 0x00 0xE001 0020
IntClr
Start
R/W 0x10 0xE001 0028
- R/W 0x80 0xE001 0030