Table of Contents
Advertisement
Music Shield User Manual
address. After the address has been read in, any further data on SI is ignored by the chip. The 16-bit
data corresponding to the received address will be shifted out onto the SO line.
XCS should be driven high after data has been shifted out.
DREQ is driven low for a short while when in a read operation by the chip. This is a very short
time and doesn't require special user attention.
SCI Write
XCS
0
1
2
SCK
SI
0
0
0
instruction (write)
SO
0
0
0
DREQ
VS1053b registers are written from using the following sequence. First, XCS line is pulled low to
select the device. Then the WRITE opcode (0x2) is transmitted via the SI line followed by an 8-bit word
address.
After the word has been shifted in and the last clock has been sent, XCS should be pulled high to
end the WRITE sequence.
2.3. SCI Register
VS1053 has 16 SCI registers in total. They are used to control the operation of VS1053b, as
shown in the following figure:
Reg
Type
Reset
0x0
rw
0x4800
0x1
rw
0x000C
0x2
rw
0x3
rw
Revision 1.1. Date: December 7, 2015. Author: W. L. Yan. Editor: Felix.
3
4
5
6
7
8
9
10 11 12 13
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
(See the Figure 7 of VS1053b datasheet)
SCI registers, prefix SCI_
Time
Abbrev[bits]
80 CLKI
MODE
80 CLKI
STATUS
0
80 CLKI
BASS
0
1200 XTALI
CLOCKF
14 15 16 17
15 14
3
2
1
0
0
address
0
0
0
0
0
0
0
Description
Mode control
Status of VS1053b
Built-in bass/treble control
Clock freq + multiplier
share awesome hardware
30 31
1
0
X
data out
0
0 X
execution
4
Advertisement
Table of Contents
