Schematics - ZiLOG Z8F08A28100KITG User Manual

Schematics

Figure 3 and Figure 4
5
R7 R7
D2 D2
PA6_nT1OUT
1 2
100 100
GREEN GREEN
R8 R8
D3 D3
PA7_T1OUT
1 2
YELL YELL 100 100
D
R10 R10
D4 D4
PC3_COUT
1 2
RED RED 10 10
VCC_33V
VCC_33V
GND
GND
NOTE 3:
Resistors R20 and R21 are not populated. See Note 2.
PA0_T0IN_JP
PA1_T0OUT_JP
C
R20 R20 R21 R21 20 pin footprint
U6 U6
PB1_ANA1
1
PB1/ANA1
PB2_ANA2
2
PB2/ANA2
0 0 0 0 PB3_ANA3
3
PB3/CLKIN/ANA3
VCC_33V
4
VDD
PA0_T0IN
5
PA0/T0IN/T0OUT/XIN/
PA1_T0OUT
6
PA1/T0OUT/XOUT
GND
7
GND
PA2
8
PA2/DE
PA3_CTS0
9
PA3/CTS0
PA4_RXD0
10
PA4/RXD0
Z8F04xA Z8F04xA
R14 R14 R15 R15
0 0 0 0
R18 R18
B
1M 1M
Y1 Y1
1 3
1 3
C19 C19 C20 C20
20 MHz 20 MHz
NOTE 2
TABLE 2
Clock Mode R14 R15 R18
Internal Only none none none
A Crystal 0 Ohm 0 Ohm none
Ceramic Res 0 Ohm 0 Ohm none
External CMOS none none none
(Use PA0_T0IN
pin on JP2)
5
UM018606-0109
on page 10 display the schematics for Z8 Encore! XP F082A Series development board.
4
R9 R9
SW2 SW2
VCC_33V GND
TEST
100K 100K
R11 R11
100 100
PA2
NOTE 1:
R12 R12
0 0
U8 U8
VCC_33V
1 3
IO IO
EMI Filter EMI Filter
SENSE
PB0_ANA0
20
PB0/ANA0
PC3_COUT
19
PC3/COUT/LED
PC2_ANA6
18
PC2/ANA6/LED
PC1_ANA5 C23 C23 C22 C22
17
PC1ANA5/CINN/LED
PC0_ANA4 + +
16
PC0/ANA4/CINP/LED
DBG 0.033uF 0.033uF C21 C21 C10 C10
15
DBG
PD0 30uF 30uF
14
RESET/PD0
PA7_T1OUT 0.033uF 0.033uF 0.001uF 0.001uF
13
PA7/T1OUT
PA6_nT1OUT
12
PA6/T1IN/T1OUT
PA5_TXD0
11
PA5/TXD0
PA3_CTS0
PA4_RXD0
PA5_TXD0
R16 0 R16 0 R17 0 R17 0
GND
NOTE 1:
PB0_ANA0 PB1_ANA1
C11 C11
0.001uF 0.001uF
Note 2: The XP supports internal, external crystal, external
C19 C20 Y1
ceramic resonator, external R/C and external CMOS drive
clock modes. R14, R15, R18, C19, C20 and Y1 are used to
none none none
support the clock mode selected.
shipped configured for external 20MHz ceramic resonator or
Yes Yes Yes
internal clock operation. When using Internal oscilator,
none none Yes
pins 7 and 8 could be used as GPIO ports PA0 and PA1. To do
so install R20 and R21.
none none none
Table 2 shows the recommended clock mode configurations.
4
Figure 3. Schematic, Z8 Encore! XP
3
Note 1:
PB6 and PB7 are dual function pins (GPIO or Analog
R12, R13, R16, and R17 are zero-ohm resistors used in
conjunction with GPIO Control Registers to select function
desired. C21, C22, and C23 are bypass capacitors that are used
for better noise rejection. U8 is an optional filter that can
be used to improve the quality of the Analog Supply. The
development board is shipped configured for Analog Supply.
Table 1 shows the configurations recommended
TABLE 1
R12 R13 R16 R17 R22 U8
GPIO OUT IN OUT IN IN OUT
Analog IN OUT IN OUT OUT optional
Supply
SW1 SW1
GND
RESET/TEST2
R13 R13
JP5 JP5
PB6
1
R22 R22 2
0 0
0 0 PB5_JP HEADER 2 HEADER 2
28 pin footprint
U5 U5
PB2_ANA2 PB1_ANA1
1 28
PB2/ANA2 PB1/ANA1
PB4_ANA7 PB0_ANA0
2 27
PB4/ANA7 PB0/ANA0
PB5 PC3_COUT
3 26
PB5/Vref PC3/COUT/LED
PB3_ANA3 PC2_ANA6
4 25
PB3/ANA3/CLKIN PC2/ANA6/LED
PC1_ANA5
5 24
PB6(AVDD) PC1/ANA5/CINN/LED
VCC_33V PC0_ANA4
6 23
VDD PC0/ANA4/CINP/LED
PA0_T0IN
7 22
PA0/T0IN/T0OUTXIN DBG
PA1_T0OUT
8 21
PA1/T0OUT/XOUT RESET/PD0
GND
9 20
GND PC7/LED
10 19
PB7(AGND) PC6/LED
PA2
11 18
PA2/DE PA7/T1OUT
PA3_CTS0
12 17
PA3/CTS0 PC5/LED
PA4_RXD0
13 16
PA4/RXD0 PC4/LED
PA5_TXD0 PA6_nT1OUT
14 15
PA5/TXD0 PA6/T1IN/T1OUT
Z8F04xA_28 Z8F04xA_28
PB7
PB2_ANA2 PB3_ANA3 PC0_ANA4 PC1_ANA5 PC2_ANA6 PB4_ANA7
C12 C12 C13 C13 C14 C14 C15 C15 C16 C16 C17 C17
0.001uF 0.001uF 0.001uF 0.001uF 0.001uF 0.001uF 0.001uF 0.001uF 0.001uF 0.001uF 0.001uF 0.001uF
J2 J2
PB0_ANA0
1
PB1_ANA1
3
PB2_ANA2
5
PB3_ANA3
7
PC0_ANA4 9
PC1_ANA5
11
The development board is
PC2_ANA6
13
PB4_ANA7
15
HEADER 8X2 HEADER 8X2
3
®
F082A Series MCU Development Board
®
Z8 Encore! XP F082A Series Development Kit
2 1
If Module is plugged onto the Dev Platform the local
supply)
RS232 interface is disabled by pin 50 of JP2
JP2 JP2
connector 2
PB4_ANA7 PC2_ANA6
1 2
PC1_ANA5 3 4 PC0_ANA4
PB3_ANA3 PB2_ANA2
5 6
PB1_ANA1 PB0_ANA0
7 8
VCC_33V 9 10
PC4
11 12
PC7
13 14
PC3_COUT
15 16
PA6_nT1OUT
17 18
GND
19 20
PA7_T1OUT
21 22
C21...C23
23 24
25 26
OUT
27 28
29 30
IN
31 32
PA3_CTS0
33 34
PA4_RXD0
35 36
37 38
GND
39 40
41 42
43 44
R19 10K R19 10K
PB6
45 46
PB7
47 48
49 50
-DIS_IrDA
51 52
-RESET
53 54
VCC_33V
55 56
57 58
VCC_33V
59 60
HEADER 30x2/SM HEADER 30x2/SM
connector 1
for
DBG
DBG
PD0
reference
PC7
PC6
only
PA7_T1OUT JP1 JP1
PC5
PC4
1 2
3 4
-TRSTN
5 6
-F91_WE 7 8
GND VCC_33V
9 10
A6 A0
11 12
A10 A3
13 14
GND VCC_33V
15 16
A8
17 18
A13
19 20
A15 A14
21 22
A18 A16
23 24
A19
25 26
A2 27 28
A11
29 30
A4
31 32
C18 C18 A5
33 34
0.001uF 0.001uF
-DIS_FLASH
35 36
A21 VCC_33V
37 38
GND A22
39 40
-CS0 41 42
-CS2
43 44
D1
45 46
D3 47 48
D5
49 50
D7
51 52
-MREQ
2 53 54
GND
4 55 56
-WR
6 57 58
-BUSACK
8 59 60
10
12
14
HEADER 30x2/SM HEADER 30x2/SM
16
Title Title Title
XP 4K MDS Processor Module. Schematic. XP 4K MDS Processor Module. Schematic. XP 4K MDS Processor Module. Schematic.
Size Size Size Document Number Document Number Document Number
B B B
96C0941-001 96C0941-001 96C0941-001
Date: Date: Date: Tuesday, March 18, 2008 Tuesday, March 18, 2008 Tuesday, March 18, 2008 Sheet Sheet Sheet
2 1
User Manual
9
GND
PC5
PC6
PB5_JP D
PA0_T0IN_JP
PA1_T0OUT_JP
PA2
PD0
GND
PA5_TXD0
GND
-DIS_232
-DIS_IRDA
GND
C
A7
A9
B
GND
A1
A12
A20
A17
A23
-CS1
D0
D2
D4
GND
D6
-IOREQ
-RD
-INSTRD
-BUSREQ
A
Rev Rev Rev
D D D
2 2 2 of of of 3 3 3
Schematics