NEC AccuSync LCD72VM User Manual page 118

Pin name I/O
RED+
RED-
GREEN+
GREEN-
BLUE+
BLUE-
HSYNC
VSYNC
TCLK
XTAL O
RESETn
PBIAS O
PPWR O
GPIO1/PWM1 O
GPIO1/PWM1 O
CLKP_LV_E O
CLKP_LV_E O
AVDD_RPLL_33
VDD_RPLL_18
VDDA_ADC_33
VDD_ADC_18
AVDD_LV_33
AVDD_OUT_LV_33
RVDD_33
CVDD_18
NO
I 77
I 78
I 74
I 75
I 70
I 71
I 95
I 96
I 88
87
I 90
29
30
53
52
7
8
I 89
I 84
I 69/79
I 82
I 1
I 4/16/28
I 33/51/94
I 31/47/65/67/92/99
Positive analog input for RED channel
Negative analog input for RED channel
Positive analog input for GREEN channel
Negative analog input for GREEN channel
Positive analog input for BLUE channel
Negative analog input for BLUE channel
ADC input horizontal sync
ADC input vertical sync
Reference clock from the crystal oscillator or external
MCU source
Crystal oscillator output
Hardware Reset signal I/O is active low output (120ms)
provided for other system components
Panel Bias Control (backlight enable)
Panel Power Control
Volume Control
Panel Backlight Control
LVDS Clock+
LVDS Clock-
Analog power (3.3v) for the reference DDS PLL
Digital power (1.8v) for RCLD and clock generator
Analog power (3.3v) for the ADC
Digital power (1.8v) for ADC encoding logic
Analog 3.3v supply for LVDS PLL and Band gap
Digital 3.3v supply for LVDS outputs
Ring VDD (3.3V)
Core VDD (1.8V)
7-3
Describe