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SiI9185A 3:1 HDMI 1.3 Switch
Preliminary Data Sheet
Silicon Image, Inc.
Transmitter Block
The Transmit block consists of a fully compliant, HDMI 1.3 transmitter. This transmitter re-transmits the data received
by the selected receiver port.
CEC Interface
The Consumer Electronics Control (CEC) Interface block provides CEC electrically compliant signals between CEC
devices and a CEC master. It allows products to meet the electrical specifications of CEC signaling by translating the
LVTTL signals of an external microcontroller (CEC host-side or Tx-side) to CEC signaling levels for CEC devices at the
Rx-side, and vice versa.
Additionally, a CEC controller compatible with the Silicon Image CEC API is included on-chip. This CEC controller has
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a high-level register interface accessible through the I
C interface which can be used to send and receive CEC
commands. This controller makes CEC control very easy and straightforward, and removes the burden of having a host
CPU perform these low-level transactions on the CEC bus.
In order to use the high-level CEC API, the host must perform a calibration of the internal CEC clock inside the
SiI9185A. This calibration is performed by setting the calibration bit, and then sending a 10ms pulse (±1%) on the
CEC_D signal input to the SiI9185A. The SiI9185A uses this pulse to calibrate an internal clock that is then used to
generate all CEC timing to guarantee CEC compliance to the HDMI specification. This calibration must be repeated at
time intervals corresponding to changes in temperature of 15°C.
EDID RAM Block
The EDID RAM block consists of 256 bytes of RAM that is shared by all ports. This means the timing information must
be identical among all the ports if the internal EDID is used. Independent registers for the CEC physical address and
checksum values for each port are also included, as these are unique to each port. On-board logic controls arbitration
when reading the 256 bytes of EDID RAM, CEC physical address, and checksum values. This allows simultaneous reads
of all ports from three different source devices if they are connected and attempt an EDID read at the same time.
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The internal EDID can be selected on a per-port basis using registers on the local I
C bus. For example: Port 0 and Port 1
can use the internal EDID, and Port 2 can use a discrete EEPROM for the EDID.
Configuration Block
The Configuration block is used to configure and control the operation of the SiI9185A. The SiI9185A has two modes of
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operation: I
C and Standalone. In I
C mode, all functions of the SiI9185A are controlled and observed with I
C registers.
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All of these registers are accessible over the local I
C Interface. These registers are used to perform port select, HPD
control, CEC control, EDID loading, and power-down control.
In Standalone mode, all functions are controlled and observed by using pins on the SiI9185A. The mode is determined
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by the level of the I2CSEL/INT pin at the rising edge of RESET#. A high indicates I
C mode, and a low indicates
Standalone mode. In Standalone mode, the SiI9185A operates independently, and has no need for an external
microprocessor.
Figure 5. Standalone Mode Configuration
SiI-DS-1016-0.80
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© 2007 Silicon Image, Inc. CONFIDENTIAL
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