Spectral Sensors and Linear Image Arrays PC/AT-ISA Interface Electronics PD-ISA16V3 Technical Documentation Board: PD-ISA16V3-2 (06010.35 / 06010.36) PLD: tim.602 / tim.507 / adrisav3 Document: Part ‚I’, Version 3.21_E, 09.11.00 18:24 tec5 AG In der Au 25 D - 61440 Oberursel / Taunus...
Technical Documentation V3.21_E I.1 General The PC/AT Interface Electronics type PD-ISA16V3 is part of the PC/AT Operating Electronics for Spectral Sensors or MOS Linear Image Sensors. Functionally, it allows the PC to control the Front End Electronics, to which the currently used Spectral Sensor is connected.
PC Interface Electronics PD-ISA16V3 Technical Documentation V3.21_E The following table shows the possible data transfers between the PC and the components of the PC/AT Interface Board (overview): I/O - address data word length transfer direction component addressed Base + 00 HEX...
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PC Interface Electronics PD-ISA16V3 Technical Documentation V3.21_E Signal assignment for control port #1: data bit signal comment designation STOR_E1# store enable 1, enables data storage FIFO_R# FIFO reset, erases FIFO memory STSCAN1# start scan 1, rising edge activates a scan cycle...
PC Interface Electronics PD-ISA16V3 Technical Documentation V3.21_E Signal assignment for the status port: data bit signal comment designation IRQIN1 internal interrupt request EXTIRQIN external interrupt request FULL# FIFO full, FIFO memory full EMPTY# FIFO empty, FIFO memory empty SCANRUN scan running, readout of the array active...
5:8K*9] or type IDT720x, x designates the storage capacity of the component [3:2K*9 / 4:4K*9 / 5:8K*9 / 6:16K*9]). The PC/AT Interface Electronics PD-ISA16V3 in standard version is equipped with 2 chips type SN74ACT7203 or IDT7203 (organization 2 KByte * 9, IC7 and IC8) in plug-in sockets. For larger memory capacity, the 2 kByte - IC's may be replaced by equivalent types, which are compatible in pin assignment and functionality, offering larger memory sizes (currently available for up to 16 kBytes).
PC Interface Electronics PD-ISA16V3 Technical Documentation V3.21_E I.3.6 Scan Cycle Clocking, Timer The term scan cycle stands for a single reset procedure for the charges on the photodiode array (read-out procedure without data storage) and one or more read-out procedures with spectral data storage, sequenced with a delay of one integration period each time.
PC Interface Electronics PD-ISA16V3 Technical Documentation V3.21_E Mode of Operation 'TimerContinuous' (Timer Mode 3): TIMSELM0 = High TIMSELM1 = High The scan cycle is controlled autonomously by the PC Interface Board. The behavior in the mode of operation 'TimerContinuous' resembles the mode of operation 'TimerSingle'.
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PC Interface Electronics PD-ISA16V3 Technical Documentation V3.21_E mode IRQ-SEL-1 IRQ-SEL-0 signal source comment TIM-IRQ via IC4B as output timer-IC #2 / timer 2, EOS/TIM# application-specific function High HALF FIFO memory half full (only FIFO IDT720x) High EMPTY# FIFO memory not empty...
PC Interface Electronics PD-ISA16V3 Technical Documentation V3.21_E I.3.8 Internal and External Scan Cycle Triggering / Chopper Operation A scan cycle may be triggered under PC-control (internally) or via external control signals. The control signals STS-SEL0 and STS-SEL1 select one of three scan cycle trigger procedures, which are explained in the following.
PC Interface Electronics PD-ISA16V3 Technical Documentation V3.21_E external scan trigger signal STSCAN8# is also routed to the status port on the PC Interface Board, allowing e. g. to monitor the chopper rate with the PC. Furthermore, the PC - Interface Electronics offers the possibility to determine whether a full scan cycle could be performed in chopper mode in the corresponding phase (illuminated or darkened).
PC Interface Electronics PD-ISA16V3 Technical Documentation V3.21_E I.5 Board Settings I.5.1 I/O Base Address (Dip Switch Block SW1) Adressbit 2** The I/O base address of the plug-in board is set by switches 1...6 of the DIP switch block (ON corresponds to Low).
PC Interface Electronics PD-ISA16V3 Technical Documentation V3.21_E I.5.3 Wait States (Jumper 3) With jumper J3 closed, the PC Interface Board activates the signal 0WS# at each access. 0WS# The activation of the signal 0WS# (zero wait states) shortens memory or I/O access times by omitting waits normally inserted to the CPU cycles.
PC Interface Electronics PD-ISA16V3 Technical Documentation V3.21_E I.7.3 Connector J2 (Service Connector) Connector type: socket connector, pin contacts pin number signal designation explanation STSCAN6# start pulse for read-out of the array SCANRUN read-out of the array running clock signal 1PIXEL#1...
PC Interface Electronics PD-ISA16V3 Technical Documentation V3.21_E I.8 Standard Version, Jumper and Solder Bridges Fig. I 4: View of the PC/AT Interface Electronics, components side, default settings for jumpers and solder bridges Fig. I 5: View of the PC/AT Interface Electronics, solder side, default settings for jumpers and solder...
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