Pioneer DV-S755AI Service Manual page 140

1
Pin Name
A
AVDD
PLL_VDD
Regulator Pins
REG_ENZ
B
REG_OUT0
REG_OUT1
REG_OUT2
External CPU Interface Pins
MCIF_ACKZ
C
MCIF_ADDR1
D
MCIF_ADDR10
MCIF_ADDR2
MCIF_ADDR3
MCIF_ADDR4
MCIF_ADDR5
MCIF_ADDR6
MCIF_ADDR7
MCIF_ADDR8
MCIF_ADDR9
E
F
140
1
2
Pin No I/O Description
23, Analog Power Supply. Must be set to 3.3V nominal.
28,
32,
41,
48
51 PLL Power Supply. Must be set to 3.3V nominal.
73 I Internal Regulator Enable. The iceLynx-Micro core voltage is
1.8V. Internal regulators are used to regulate the 3.3V VDD
inputs to 1.8V. This pin enables the regulators.
74 O 1.8V Regulator Output. This pin should be connected to
ground using a 0.1uF capacitor.
115 O 1.8V Regulator Output. This pin should be connected to
ground using a 0.1uF capacitor.
160 O 1.8V Regulator Output. This pin should be connected to
ground using a 0.1uF capacitor.
95 I/O MCIF Acknowledge pin. Default active low. iceLynx-Micro
asserts this signal if it has completed the MCIF request. This
signal is always driven. This signal is used for the following
modes:
•
•
In Serial MCIF Mode, this pin is used for the Serial Read
Acknowledge (SMCIF_RACKZ.)
120 I MCIF Address 1 pin. This data pin is the least significant bit of
the MCIF Address Bus.
MCIF_ADDR0 is internally grounded. Only 16-bit addressing
is allowed. MCIF_ADDR1 should be connected to the
Address1 signal of the system CPU.
129 I MCIF Address 10 pin. This data pin is the most significant bit
of the MCIF Address Bus.
121 I MCIF Address 2 pin
122 I MCIF Address 3 pin
123 I MCIF Address 4 pin
124 I MCIF Address 5 pin
125 I MCIF Address 6 pin
126 I MCIF Address 7 pin
127 I MCIF Address 8 pin
128 I MCIF Address 9 pin
DV-757Ai
2
3
68000 + Wait I/O Access
MPC850 I/O Access
3
4
4