Pioneer DV-S755AI Service Manual page 139

5
¶ Pin Function
Pin Name
Power & Ground Pins
DISABLE_IFZ
HPS
LOW_PWR_RDY
WTCH_DG_TMRZ
RESET_ARMZ
RESETZ
VSS
AGND
PLL_GND
VDD
5
6
Pin No I/O Description
64 I Interface Disable. When asserted, the interfaces are put into
a Hi-Z state. Interfaces include: ex-CPU, HSDI, GPIO, and
WTCH_DG_TMRZ.
62 I Host Power Status. This indicates the power status of the
external system to iceLynx-Micro. A rising edge indicates the
system CPU has been turned ON. (The internal ARM should
wake up.) A falling edge indicates the system CPU has been
turned OFF. (The internal ARM decides if power down is
necessary.)
63 O Output to system to indicate iceLynx-Micro is ready to go into
a low power state. The ARM and WTCH_DG_TMRZ control
this pin.
88 O Watch Dog Timer (for the ARM.) iceLynx-Micro hardware
asserts this pin whenever ARM software has not updated the
Timer2 register within the allowed time period.
60 I ARM reset. This signal resets the internal ARM processor.
59 I/O Device reset. This signal resets all logic. This includes the
PHY, Link core, memory, the ARM, and random logic.
1, Digital Ground.
21,
55,
76,
102
117
131,
146,
162
176
24, Analog Ground.
27,
35,
45,
54 PLL Ground.
4, Digital Power Supply. Must be set to 3.3V nominal.
20,
56,
75,
101
116,
130
145,
161
175
6
7
DV-757Ai
7
8
A
B
C
D
E
F
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