Alignment Procedure - NAD T955 C Service Manual

ALIGNMENT PROCEDURE

A. DC OFFSET VOLTAGE
The DC OFFSET between OFFSET Test Point and AGND must be within 0+/-20mV.
B. IDLING CURRENT
The idling current in the output stage of the poweramp should be set to 25mA+/-5mA per
pnp-npn transistor pair( This means the mid point voltage is 4mV with down limit of 3mV
and up limit of 5mV). The alignment procedure is: At first, adjust RV103 (Marked as "Idling
Current ADJ" in the drawing below) for a voltage of 4mV +/- 1mV between Test point 1 and
2. Then pre heat the unit for 5 minutes, let idling current settled and then readjust to 4mV +/-
1mV.
Pls note: Though the idling current is set as 4mV +/-1mV during the adjustment, due to the
influence of varied ambient temperature and mains voltage etc., the idling current will drift after
some time. During the normal checking of idling current in the service field, it's acceptable as
long as the voltage is in the range of 3mV—5mV.
C. ISC SENSITIVITY
The ISC sensing voltage can allow 0mV+/-50mV. But, for the alignment process in our
factory, we tighten the limit to 0mV+/-10mV. That is to adjust Pot RV104 (as marked as
"ISC SENS ADJ" in the below drawing) to get a voltage between the "ISC SENSE TEST
POINT" and AGND to be 0mV+/-10mV.
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