Philips CE130/55 Service Manual page 59

1 Semiconductor
Bank Interleave Page Read Cycle @CAS Latency=2, Burst Length=4
0 1 2 3
CLK
CKE
∗Note 1
CS
RAS
CAS
ADDR RAa CAa
A11
A10 RAa
DQ
WE
UDQM,
LDQM
Row Active
(A-Bank)
Read Command
(A-Bank)
*Note: 1. CS is ignored when RAS, CAS and WE are high at the same cycle.
4 5 6 7 8
RBb CBb
RBb
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
Row Active
(B-Bank)
Read Command
(B-Bank)
9 10 11 12 13 14
High
CAc CBd
Read Command
(B-Bank)
Read Command
(A-Bank)
FEDD56V16160F-02
MSM56V16160F
15 16 17 18 19
CAe
I
ROH
Precharge Command
(A-Bank)
Read Command
(A-Bank)
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