Philips CE130/55 Service Manual page 55

1 Semiconductor
Page Read & Write Cycle (Same Bank) @CAS
0 1 2 3
CLK
CKE
CS
Bank A Active
RAS
CAS
I
CCD
ADDR
Ca0
A11
A10
DQ
WE
UDQM,
LDQM
Read Command
Read Command
*Note: 1. To write data before a burst read ends, UDQM and LDQM should be asserted three cycles prior to the
write command to avoid bus contention.
2. To assert row precharge before a burst write ends, wait t
Input data during the precharge input cycle will be masked internally.
CAS Latency= = = = 2, Burst Length=4 CAS CAS
4 5 6 7 8
High
Cb0
Qa0 Qa1 Qb0 Qb1
l
OWD
∗Note 1
Write Command
9 10 11 12 13
Cc0 Cd0
Dc0 Dc1 Dd0
t
WR
∗Note 2
Precharge Command
Write Command
after the last write data input.
WR
FEDD56V16160F-02
MSM56V16160F
14 15 16 17 18 19
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