Pci-Das1200/Jr Block Diagram - Measurement Computing PCI-DAS1200/JR User Manual

PCI-DAS1200/JR User's Guide

PCI-DAS1200/JR block diagram

PCI-DAS1200/JR functions are illustrated in the block diagram shown here.
Burst/Scan
Analog In
16 CH S.E.
8 CH DIFF.
Gains = 1, 2, 4, 8
Digital I/O
FIRSTPORTA
FIRSTPORTA(7:0)
FIRSTPORTB
FIRSTPORTB(7:0)
FIRSTPORTCH
FIRSTPORTCH(3:0)
FIRSTPORTCL
FIRSTPORTCL(3:0)
Gain and Offset Autocal
Mux
12-Bit, 330KHz
&
Start EOC
Gain
ADC
Pacer
CTR 2
CTR 1
EXT PCR
Sample 10 MHz
Counter
CTR0
Control
INT
XTRIG
Decode/Status
8
Boot
EEPROM
CONTROLLER
Figure 1. PCI-DAS1200/JR functional block diagram
1024 x 12
FIFO
Burst/Scan
CONTROLLER
FPGA
Scan
ADC
DAC
&
Pacer
Control
Burst
Logic
Trigger
Control
INT
Int
Ctl
Bus
Timing
Local Bus
BADR1
BADR2
PCI
BADR3
BADR4
Interrupt
PCI Bus(5V, 32-bit, 33 MHZ)
8
Introducing the PCI-DAS1200/JR
CLK2
GATE2 CTR2
OUT2
CLK1
CTR1
GATE1
OUT1
ADC
INT
Index
XTRIG
Counter
User
CTR 0
GATE
CLK
OUT
Time Base 10 MHz
PC I-DAS1200 and PC I-DAS1200/JR
block diagram