Cpu Port Allocation - Icom IC-RX7 Service Manual Addendum

4-6 CPU PORT ALLOCATION

Pin LINE
No. NAME
1 KR0 Key matrix.
+3V line SW
2 PCON
"L"=Power ON
Tone fi lter (L: IC12) SW
3 TCON
"L"=Filter activated.
4–7 KS0–KS3 Key matrix.
Tone control circuit SW.
8 TREBLE_B
"H"=Treble-B
Tone control circuit SW.
9 BASS_B
"H"=Bass-B
10 ESIO EEPROM data I/O.
11 ECK EEPROM clock.
Tone control circuit SW.
13 TREBLE_C
"H"=Treble-C
Tone control circuit SW.
15 BASS_C
"H"=Bass-C
AF fi lter (L: Q20) by-pass SW.
16 TRUTH
"H"=FM mode.
RX frequency shift.
17 SHIFT
"L"=200 MHz RX.
18 LCK DAC (L: IC16) clock.
AF line SW (M: IC9) control.
19 AM
"L"=Receiving in AM mode.
AGC function switching.
20 AGCC
"L"=AGC activated.
RX mode switching (phase shifter
21 WFM switching; discriminator/LC resonator).
"H"= WFM mode.
AM broadcast antenna switching.
22 ANTSW
"L"=Internal bar antenna.
RF circuit (BC band) control.
23 B2C
"L"=BC band RX (Ext. LOCAL antenna).
RF circuit (SW band) control.
24 B1C
"L"=SW band RX (Ext. DX antenna).
Attenuator (M: D2, R2 to 4) control.
25 ATT
"L"=Attenuator ON.
26 NOISE Detected noise level (D/A value).
RF circuit (800 MHz band) control.
27 800MC
"L"=800 MHz band RX.
RF circuit (1 GHz band) control.
28 GC
"L"=1 GHz band RX.
RF circuit (UHF band) control.
29 UHFC
"L"=UHF band RX.
Earphone antenna control.
30 EAR
"L"=Earphone antenna activated.
34 DUD [DIAL] (rotary encoder; L S21)
35 DCK [DIAL] (rotary encoder; L S21)
36 LDATA DAC (L: IC16) data.
CPU clock signal to converter (L: IC11,
37 CKO
D24–27).
38 POWER [POWER] key.
39 DATAC Common data to the buffer (L: IC1).
LCD backlight driver (L: Q5) control.
40 LIGHT
"H"=Backlight (L: DS10 to 12) ON.
AF power AMP SW (L: Q11, 12) control.
41 AFON
"H"=AF power AMP (L: IC9) ON.
44 BEEP Beep sounds (square waves).
45 RSSI RSSI voltage (A/D value).
46 RTONE Demodulated tone signals.
DESCRIPTION
Pin LINE
I/O
No. NAME
47 CTONE
I
48 VSCAF
O
49 CHG
O
I
50 TEMP
O
51 BATTI
52 HVIN
O
59 RESET
I/O
CPU
O
70 CLOCK
O
SHIFT
O
71 VCO1
O
72 VCO2
O
O
73 VCO3
O
O 74 VCO4
O
75 BDET
76 LCDDT
O
77 LCDCS
78 LCDCK
O
79 CL_OUT
80 CL_IN
O
83 DASTB
O
84 VRSTB
85 PCK
I
86 PLDATA
O
87 PSTB1
88 PSTB2
O
89 PS
O
90 CHGC
O
91 HVDET
I
I
92 CL_IN
I
93 VHF_C
O
94 HFC
I
O
95 R3C
O
96–
O
KR5–KR1
100
I
I
I
4 - 5
DESCRIPTION
Demodulated tone signals.
Filtered demodulated signal (extracted
voice signal).
Charge status.
"H"=While pre/fast charging.
Internal temparature according divided
voltage by thermister (L: R189)
Battery voltage input (AD value).
DC input voltage monitor (divided
voltage of HV line).
CPU reset signal.
CPU clock frequency shift.
VCO switching signal.
"L"= VCO1 activated (=receiving
741 MHz
).
VCO switching signal.
"L"= VCO1 activated (=receiving
510 MHz/1130–1368 MHz
VCO switching signal.
"L"= VCO1 activated (=receiving
283 MHz/950–1130 MHz
VCO switching signal.
"L"= VCO1 activated (=receiving
83.5 MHz/741–950 MHz
Battery pack attachment detect.
"L"=Battery pack is attached.
Serial data to the LCD (L: DS13).
Serial data to the LCD (L: DS13).
Serial clock to the LCD (L: DS13).
Cloning data.
Cloning data.
Strobe to the DAC (L: IC16).
Strobe to the VR IC (L: IC10).
PLL clock.
PLL data.
PLL (1st VCO UNIT; IC3) strobe.
PLL (2ND VCO UNIT; IC1) strobe.
Power save mode control for PLL IC.
"L"=While in power save mode.
Charge management IC (L: IC18) control.
"H"=While charging.
HV line voltage detect.
"H"=3 V is applied.
Cloning data.
RF circuit (VHF band) control.
"L"=VHF band RX.
RF circuit (HF band) control.
"L"=HF band RX.
R3V line SW. (regurator (L: IC4) control
signal)
"H"= R3V line is ON. (the regulator is
enable)
Key matrix.
I/O
I
I
I
I
I
I
I
O
510–
O
283–
O
).
83.5–
O
).
0.15–
O
).
I
O
O
O
O
I
O
O
O
O
O
O
O
O
I
I
O
O
O
I