Philips SACD 1000/001 Service Manual page 86

GB 130 9. SACD 1000
PIN DESCRIPTIONS
PIN NUMBERS SYMBOL
35
34 CKE
18
15, 16, 17 WE#, CAS#,
RAS#
14, 36 DQML,
DQMH
19
21-24, 27-32, 20 A0-A10
2, 3, 5, 6, 8, 9, DQ0-
11, 12, 39, 40, 42, DQ15
43, 45, 46, 48, 49
33, 37
7, 13, 38, 44 V
4, 10, 41, 47 V
1, 25
26, 50
Circuit-, IC descriptions and list of abbreviations
TYPE
CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all banks idle), ACTIVE POWER-DOWN (row ACTIVE
in either bank) or CLOCK SUSPEND operation (burst/access in progress).
CKE is synchronous except after the device enters power-down and self
refresh modes, where CKE becomes asynchronous until after exiting the
same mode. The input buffers, including CLK, are disabled during power-
down and self refresh modes, providing low standby power. CKE may be tied
HIGH.
CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
Input Command Inputs: RAS#, CAS# and WE# (along with CS#) define the
command being entered.
Input Input/Output Mask: DQM is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked when DQM is
sampled HIGH during a WRITE cycle. The output buffers are placed in a
High-Z state (two-clock latency) when DQM is sampled HIGH during a READ
cycle. DQML corresponds to DQ0-DQ7; DQMH corresponds to DQ8-DQ15.
DQML and DQMH are considered same state when referenced as DQM.
BA Input Bank Address Inputs: BA defines to which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied. BA is also used to program the
twelfth bit of the Mode Register.
Input Address Inputs: A0-A10 are sampled during the ACTIVE command (row-
address A0-A10) and READ/WRITE command (column-address A0-A7, with
A10 defining AUTO PRECHARGE) to select one location out of the 512K
available in the respective bank. A10 is sampled during a PRECHARGE
command to determine if all banks are to be precharged (A10 HIGH). The
address inputs also provide the op-code during a LOAD MODE REGISTER
command.
Input/ Data I/Os: Data bus.
Output
NC – No Connect: These pins should be left unconnected.
Q Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
DD
Q Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
SS
Supply Power Supply: +3.3V ±0.3V.
V
DD
V Supply Ground.
SS
DESCRIPTION
16Mb: x16
SDRAM