Philips SACD 1000/001 Service Manual page 63

in which the pattern recorded in the previous stage is read
back.
During this read phase the OPC block stores A1, A2 and
CALF samples from exact the same location where during
the OPC write phase the Pw samples where stored. The
samples for A1, A2, CALF and Pw are listed side by side into
memory. After the read back phase the processor calculates
at which setting of alpha0 the least jitter is encountered.
This setting will be used to write the disc with.
9.18 The OPC top level.
The OPC block as a whole has 5 possible modes:
– Recording mode: This can be either OPC writing (writing
EFM test patterns to disc and Alpha0 stepping) or
standard write mode (i.e. alpha0 is constant).
– OPC reading: Reading back OPC test patterns from disc.
– Normal read mode: detects the presence of EFM.
– DVD read mode: used for DVD-RAM experiments.
– EFMD only mode: no data being written to the AUX RAM,
but the EFM detector and the PW monitor still running.
Contents of the QUX RAM remain unchanged.
All actions in the OPC hardware are synchronised to the
ATIP frame sync, which can be either generated internally or
received from the encoder/decoder during writing. The
microprocessor writes data asynchronously to the OPC
hardware. The OPC block synchronises this data to the sync
either internally generated, or obtained from CDR60.
9.19 The Analogue to Digital converter.
The analogue to digital converter of the OPC is shared with
the ADC required by the PCS.
9.20 The digital input filters.
The combined ADC for the OPC and the PCS delivers a
multiplexed stream of 8 bit words. A sequential low-pass filter
filters this multiplexed stream. The 4 analogue multiplexed
input signals from the OPC (A1, A2, CALF and Pw) are
filtered by 4 identical LPF's. (One for each channel). This
filters can be adapted to various speeds by changing the
subsampling factor (i.e. the sample rate of the filter), the cut
off frequency scales with the sample frequency. The sample
frequency of the filter is equivalent to the OPC timebase
frequency, which is the output of the pre-scaler.
9.21 OPC demux.
The OPC demux block demultiplexes the stream supplied by
the LPF. This same block also changes the format of the
digital data from signed (representation inside the filter) to
unsigned (representation in the rest of the OPC). The
demultiplexing process introduces one baseclock delay.
9.22 The sequencer.
The OPC sequencer controls the timing of all the hardware
actions in the OPC hardware. It generates the OPC timebase
and locks it to the ATIP pulse. A programmable pre-scaler
generates the OPC timebase.
Dividing the ADC sample clock by 8 derives the input clock of
this pre-scaler. (= Identical to the sample rate per channel).
The pre-scaler can divide this clock by a number in the range
from 1-16. The division factor can be programmed via the
OPC ctrl register. The OPC timebase is locked to the
selected ATIP source, which can be either an external
ATI P sync or an internally generated sync. (Programmable).
The OPC timebase clock supplies the sample frequency for
Circuit-, IC descriptions and list of abbreviations SACD 1000
the input LPF's, the OPC pre-processor and the EFM
detector.
The sequencer controls the timing of all the hardware actions
in the OPC hardware. The sequencer is started either by an
external ATIP sync or an internally generated sync
(programmable).
All data acquisition and alpha0 settings change synchronised
to this sync signal (rising edge of the ATIP sync). An
exception on this is the switching of the ATIP input itself,
which is immediately changed whenever the bit in the OPC
ctrl register is changed. When this was latched on the ATIP
source itself, it would create a deadlock when there was no
ATIPin from CDR-60.
9.23 The Pw monitor
The Pw monitor is used during the "OPC write" and normal
write mode. The comparator compares the incoming Pw with
two programmable thresholds PW MAX and PW MIN. Both
these thresholds can be programmed via the OPC PW
register, which contains 4 bits for each threshold.
Internally both 4-bit thresholds PW MAX and PW MIN are
extended to 8 bit values. The compare function performs an
unsigned compare.
The first threshold is used to detect fingerprints. The second
is used to check the correct operation of the laser driver.
Figure 9-6 OPC PW monitor.
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