Dvio Board: Dvcodec - Philips DVDR880/001 Service Manual

Circuit Diagrams and PWB Layouts

DVIO Board: DVCODEC

1 1 1 2 2 2 3 3 3
DVCODEC DVCODEC
A A A
B B B
C C C
+3V3_DV
DV DTACKn
DV_DRQn
DV ERRn
DV LCn
+3V3_DV
HAD(0)
D D D HAD(1)
HAD(2)
HAD(3)
+3V3_DV
HAD(4)
HAD(5)
HAD(6)
HAD(7)
+3V3_DV
E E E
+3V3_DV
+3V3_DV
AUD_WS_701
F401
AUD BCLK
AUD SDI 3405
F403 47R
F F F
G G G
H H H
HAD(7:0)
{DV_LCn,DV_ERRn,DV_DRQn,DV_DTACKn,DV_ASn,DV_PDn,DV_DSUn,DV_RWn,DV_VS,DV_HS_IN,DV_RSTn,DV_HS_OUT,DV_DSLn}
{AUD_BCLK,AUD_WS_OUT,AUD_WS_701,AUD_MUTE,AUD_SDI,AUD_SDO_DAC,AUD_SDO_CON}
I I I
1 1 1 2 2 2 3 3 3
DVDR880-890 /0X1
4 4 4 5 5 5 6 6 6 7 7 7
F400
7404
NW700LQ
1
VCC3 3 1 VCC3 3 20
2
HOST 16 8 DRAM D10
3
GPIO0 DRAM D9
4
GPIO1 DRAM D8
5
DRAM DATA [ 0...31] BUS DRAM DATA [ 0...31] BUS
GPIO2 VSS19
6
GPIO3 DRAM D7
7
VSS1 VCC3 3 19
8
HOST DTAC DRAM D6
9
HOST DRQ DRAM D5
10
HOST ERR DRAM D4
11
HOST LC VSS18
12
VCC3 3 2 DRAM D3
13
HOST AD0 VCC3 3 18
14
VSS2 DRAM D2
15
HOST AD1 DRAM D1
16
HOST AD2 DRAM D0
17
HOST AD3 VSS17
18
VCC3 3 3 DRAM A8
19
HOST AD4 VCC3 3 17
20
VSS3 DRAM A7
DV Decoder DV Decoder
21
HOST AD5 DRAM A6
22
HOST AD6 DRAM A5
23
HOST AD7 VSS16
24
VCC3 3 4 DRAM A4
25
HOST AD8 VCC3 3 16
26
VSS4 DRAM A3
27
HOST AD9 DRAM A2
28
HOST AD10 DRAM A1
29
HOST AD11 VSS15
30
VCC3 3 5 DRAM A0
31
HOST AD12 VCC3 3 15
32
VSS5 DRAM WE
33
HOST AD13 DRAM LCAS
34
HOST AD14 DRAM UCAS
35
HOST AD15 VSS14
36
VCC3 3 6 DRAM RAS
37
AUD WS AUDIO AUDIO VCC3 3 14
F402 38
VIDEO BUS VIDEO BUS
VSS6 VID RDY
39 INTERFACE INTERFACE
AUD BCLK VID DTACK
40
AUD SDO VID OE
F426
5402
+3V3
100MHZ
4 4 4 5 5 5 6 6 6 7 7 7
7. EN 122
8 8 8 9 9 9 10 10 10
IO(31:0)
A(0:8)
120
+35V_DV_EDO
IO(10)
119
IO(9)
118
+VCC_DV_RAM
117 IO(8)
116
115 IO(7) 7402
114 MT4LC1M16E5
+35V_DV_EDO
IO(6)
113
Φ
112 IO(5)
IO(4)
111
EDO RAM
A(0) IO(0)
110 17 2
0 0 0 0
1Mx16 IO(1)
109 IO(3) A(1) 18 3
1 1 1 1
IO(2)
108 A(2) 19 4
+35V_DV_EDO
2 2 2 2
IO(2) A(3) IO(3)
107 20 5
3 3 3 3
IO(4)
106 IO(1) A(4) 23 7
4 4 4 4
IO(0) ADR ADR IO(5)
105 A(5) 24 8
5 5 5 5
A(6) 25 9 IO(6)
104
6 6 6 6
IO(7)
103 A(8) A(7) 26 10
7 7 7 7
IO(8)
102 +3V3_DV A(8) 27 33
DATA DATA
8 8 8 8 IO(9)
101 A(7) 28 34
9 9 9 9
IO(10)
100 A(6) 35
10 10
A(5) RASn IO(11)
99 14 36
LCASn RAS RAS 11 11 IO(12)
98 31 38
LCAS LCAS 12 12
UCASn IO(13)
97 A(4) 30 39
HCAS HCAS 13 13
WEn IO(14)
96 +3V3_DV 13 40
WE WE 14 14
IO(15)
95 A(3) 29 41
OE OE 15 15
94 A(2)
A(1)
93 15 11
92 16 NC NC 12
NC NC
91 A(0) 32
90 +3V3_DV
WEn
89
LCASn
88
UCASn
87
86
RASn
85
84
+3V3_DV
83
CRTL{RASn,LCASn,UCASn,WEn}
82
81
1Mx16 devices are used as 256kx16 1Mx16 devices are used as 256kx16
OPTION
5400
+5V
100MHZ
F416 5403
+3V3_DV +3V3
100MHZ
8 8 8 9 9 9 10 10 10
11 11 11 12 12 12 13 13 13 14 14 14
+VCC_DV_RAM
7403
MT4LC1M16E5
Φ
EDO RAM
A(0)
17 2 IO(16)
0 0 0 0
1Mx16
A(1) 18 3 IO(17)
1 1 1 1
A(2) 19 4 IO(18)
2 2 2 2
A(3)
20 5 IO(19)
3 3 3 3
A(4) 23 7 IO(20)
4 4 4 4
ADR ADR
A(5) 24 8 IO(21)
5 5 5 5
A(6) 25 9
IO(22)
6 6 6 6
A(7) 26 10 IO(23)
7 7 7 7
A(8) 27 33 IO(24)
DATA DATA
8 8 8 8
28 34
IO(25)
9 9 9 9
35 IO(26)
10 10
RASn
14 36 IO(27)
LCASn RAS RAS 11 11
31 38 IO(28)
LCAS LCAS 12 12
UCASn
30 39 IO(29)
HCAS HCAS 13 13
WEn
13 40 IO(30)
WE WE 14 14
29 41 IO(31)
OE OE 15 15
15 11
16 NC NC 12
NC NC
32
{DV_LCn,DV_ERRn,DV_DRQn,DV_DTACKn,DV_ASn,DV_PDn,DV_DSUn,DV_RWn,DV_VS,DV_HS_IN,DV_RSTn,DV_HS_OUT,DV_DSLn}
OPTION
5401
+5V
100MHZ
F425 5404
+35V_DV_EDO +3V3
100MHZ
11 11 11 12 12 12 13 13 13 14 14 14
15 15 15
2400 I6
2401 I6
2402 I6
2403 I7
2404 I7
A A A
2405 I7
2406 I8
2407 I8
2408 I8
2409 I8
2410 I10
2411 I10
2412 I11
B B B 2413 I11
2414 I11
2415 I12
2416 I13
2417 I13
2418 I14
2419 I14
2420 I14
2421 I15
C C C 3400 B4
3401-A H5
3401-B G5
3401-C H5
3401-D G5
3402-A H6
3402-B G6
3402-C H6
3402-D G6
D D D
3403 G6
3404 G7
3405 F3
5400 H10
5401 H13
5402 I5
5403 I10
5404 I13
7402 C9
E E E
7403 C11
7404 C4
F400 B4
F401 F3
F402 F4
F403 F3
F404 G6
F405 G7
F406 F5
F F F
F407 F5
F408 F5
F409 H6
F410 G6
F411 F6
F412 F6
F413 F6
F414 F6
F416 I9
G G G
F417 I15
F418 G7
F419 F6
F420 H6
F421 H6
F422 H7
F425 I12
F426 F4
H H H
YUV(7:0)
F417
+VCC_DV_RAM
I I I
CL 16532145_017.eps
221101
15 15 15