Yamaha YSP-1100U Service Manual page 62

A B C
YSP-1100
DSP 2/3
1
2
3
4
5
6
7
8
9
10
# All voltages are measured with a 10MΩ/V DC electronic volt meter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
62
D E F
3.1
3.3
0
3.3
1.3
0
3.3
3.3
3.3
3.3
0
1.3
1.7
0
1.3
0
1.7
1.7
0.8
1.6
1.7
1.3
0
1.3
0
1.6
1.3
0
DSP2
0
1.3
3.3
No replacement part available.
0
1.3
サービス部品供給なし
3.3
3.3
1.3
3.3
0
1.3
3.3
0
0
1.3
1.3
0
G H I
3.2
0.1
1.3
0
0.7
1.3
1.3
0
3.3
1.7
1.7
3.3
0.5
0
1.3
3.0
3.0
3.0
3.0
3.0
3.0
3.3
0
1.3
3.1
3.1 3.3 0
3.0 3.0 3.0
3.2 3.3 0
3.0
3.0
2.9 3.0 2.9
2.9
0 3.3
1.3 3.0 2.9
0 3.0 2.9
3.3 3.3 0
3.1 3.0 3.2
3.0
3.0 3.0
2.9 0 3.3
3.1 3.1 3.1
0 3.3 0
3.1 3.3
3.3
3.1
0 3.3 1.7
1.3
3.3
3.3
0 0
0 0
0 0
0 1.6
3.2 1.2
3.2 3.1
3.2 3.1
3.3 0
DRAM
J K L
IC12: D60YA003BPYP225
Decoder
EMIF32
McASP1
McASP0
McBSP1
McBSP0
I2C1 Enhanced
DMA
Controller
I2C0
(16 channel)
Timer 1
Timer 0
GP1
GP0
HPI16
IC13: SN74AHC1G08DCKR
2-input AND gate
A 1 5 Vcc
B 2
GND 3 4 Y
IC16: W9864G6EH-7
1M x 4 banks x 16 bits SDRAM
CLK
CLOCK
BUFFER
CKE
CS
RAS
CAS
WE
A10
MODE
A0
REGISTER
A9
A11
BS0
BS1
REFRESH COLUMN
COUNTER COUNTER
0 0
0 3.3 IC17: S29AL016D70TFI0
0 0
16M-bit COMS 3.0 volt-only boot sector flash memory
0 3.0
0 3.1
0 3.1
0 3.0
RY/ BY#
0 2.9
V
CC
0 3.0
V
2.9 SS
3.3 3.0
3.1 3.3 RESET#
2.9
3.1
3.2
WE# State
0 3.0 Contr ol
BYTE#
0 3.0
Comm and
1.6 3.0
Regi st er
1.2 3.1 PGM Vo ltage
3.1 3.0
3.1 3.3
3.2 0 CE#
OE#
3.2 3.3
3.2 0
FLASH
V De te ct or
CC
A0– A19
DSP
M N
Digital Signal Processors
L2 Cache/
L1P Cache
Memory
4 Banks Direct Mapped
64K Bytes 4K Bytes Total
Total
(4-Way)
C67x TM CPU
Instruction Fetch Control
Registers
Instruction Dispatch
Control
L2 Instruction Decode Logic
Memory
Data Path A Data Path B Test
DA610:
A Register File B Register File
192K Bytes In-Circuit
Emulation
DA601:
64K Bytes .L1t .S1t .M1t .D1 .D2 .M2t .S2t .L2t Interrupt
Control
L1D Cache
2-Way Set
R2 ROM
Associative
512K
4K Bytes Total
Bytes
Total
Clock Generator,
Oscillator and PLL Power-Down
x4 through x25 Multipliers Logic
/1 through /32 Dividers
COLUMN DECODER COLUMN DECODER
CELL ARRAY CELL ARRAY
BANK #0 BANK #1
SENSE AMPLIFIER SENSE AMPLIFIER
DQ0
DATA CONTROL DQ
CIRCUIT BUFFER
DQ15
UDQM
LDQM
COLUMN DECODER COLUMN DECODER
CELL ARRAY CELL ARRAY
BANK #2 BANK #3
SENSE AMPLIFIER SENSE AMPLIFIER
DQ0–DQ15 (A-1)
Sect or Sw itc hes
Erase V olt ag e In put/ Out put
Generat or Buff ers
Generator
Data
Chip Enab le
STB Lat ch
Out put Enable
Logic
Y-Decoder Y- Gating
STB
Tim er
X- Decoder Cell M atrix