Schematic Diagrams - Yamaha YSP-1100U Service Manual

A B C

SCHEMATIC DIAGRAMS

DSP 1/3
1
POINT B-1 Pin 13 of IC26
0.4
0
2
5,1
0
3.3
0
3.3
0
3
4
5
6
7
8
9
IC1-3: PQ1CZ41H2Z
Chopper regulators
V
V OUT
IN
1 2
Voltage ON/OFF
regulator circuit
PWM COMP. ON/OFF
5
control
Q
Overcurrent
R
detection F/F
circuit S
ERROR AMP. O
adj
4
10
V
ref
Overheat
detection
circuit
3
COM
D E F
3.3
0
0
0
0
3.3
1.5
1.6
XTAL
DIR B-1 1.6
3.3
0
F.F
3.2
3.3
0
0.1
1.3
0
3.3
3.3
3.3
0
1.3
0
1.3
0
0
0
1.7
1.3
0
1.7
3.3
0
1.3
0 DSP1
3.2
3.1
3.3
0
1.3
No replacement part available.
~
サービス部品供給なし
0
1.3
3.3
3.3
1.3
3.3
0
1.3
3.3
0
0
1.3
1.3
0
IC4: LC89057W-VF4D-E IC5: D60YA003BPYP225
Digital audio interface transceiver Decoder
EMPHA/UO AUDIO/VO INT CL CE CI XMODE
32 33 35 48 39 38 41
EMIF32
McASP1
RXOUT 1 Microcontroller
Cbit, Ubit 37 DO
McASP0
I/F
RX0 2
McBSP1
36 RERR
RX1 3
McBSP0
RX2 4
Demodulation
Input Data
RX3 5 & 21 RDATA I2C1
Selector Selector
Lock detect
RX4 8
I2C0
RX5/VI
9
24 SDIN
Timer 1
RX6/UI 10
16 RMCK Timer 0
LPF 13 PLL
17
RBCK
GP1
Clock
20 RLRCK
TMCK/PIO0 44
Selector
GP0
22 SBCK
TBCK/PIO1 45 Modulation
1/N
& 23 SLRCK
HPI16
TLRCK/PIO2 46
Parallel Port
TDATA/PIO3 47
TXO/PIOEN 48
29 28 27 34
XIN XOUT XMCK CKST
G H I
0 3.3
3.3 0
3.3 3.1
~ 3.1
3.3 0
2.5 0.7
1.3 1.7
3.3 0.7
1.7 1.7
4.1
0 0
2.6 0
2.6 5.0
0
2.6 2.5
ADC
3.3
1.7
0.1
1.7
1.3
3.3
1.3
1.3
0
3.3
0.7
1.3
0
0
0
3.3
1.7
1.7
3.3
3.3
0
3.1
3.1
3.1
3.1
3.1
3.1
3.2
0
1.3
3.1
3.1
3.1
3.1 3.3 0
3.1
3.1 3.1
3.1 3.1 3.1
3.1 0 0
1.3
3.1 3.1
0 3.1 3.1
3.3
3.3 3.3
3.1 3.1 3.1
3.1 3.1 3.1
3.1
0 0
3.2 3.1 3.1
3.1 3.1
3.2 3.3 3.3
3.3
3.2
0
3.3 3.2
1.3 3.3 1.7
3.3
3.3
1.0 0
0 0
0.1 1.0
0.2 1.1
3.1 1.5
3.1 1.9
3.3
DRAM
IC10: WM8738
24bit stereo ADC
6
AVDD 9
5
CAP
10
Digital Signal Processors AGND
L2 Cache/
7 ADC
Memory L1P Cache RIN
Direct Mapped
4 Banks
4K Bytes Total
64K Bytes
Total
(4-Way)
C67x TM CPU
Instruction Fetch Control
Registers
Instruction Dispatch
Control LIN 8 ADC
Instruction Decode
L2 Logic
Enhanced
Memory
DMA Data Path A Data Path B
Test
Controller DA610:
A Register File B Register File
(16 channel) In-Circuit
192K Bytes
Emulation
DA601:
Interrupt
64K Bytes .L1t .S1t .M1t .D1 .D2 .M2t .S2t .L2t 1 14
Control
L1D Cache
2-Way Set
R2 ROM Associative
512K
4K Bytes Total
Bytes
Total
Clock Generator,
Oscillator and PLL Power-Down
x4 through x25 Multipliers Logic
/1 through /32 Dividers
J K
IC9: W9816G6CH-7
512K x 2 banks x 16 bits SDRAM
IC11: S29AL004D70TFI0
0 0
4M-bit COMS 3.0 volt-only boot sector flash memory
0 3.3
0 0
0 3.1
1.0 3.1
0 3.1
0 3.1
0 3.1
3.1
3.1
3.3 3.1
3.2 3.3
3.1
3.1
3.1
0
3.1
0 3.1
1.0 3.1
1.1 3.1
1.5 3.1
1.9 3.3
3.1 0
3.1 3.3
0.2 0.1
FLASH
DSP
IC7: SN74LVC74APWR
Dual positive-edge-triggered D-type flip-flop
PRE
4 11
CLK C
C
CONTROL
INTERFACE
C
TG
C C
SDATO
2
C
LRCLK
12
DIGITAL AUDIO
D TG TG
FILTERS INTERFACE
3
BCLK
13 MCLK
C C
CLR
# All voltages are measured with a 10MΩ/V DC electronic volt meter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
L M N
YSP-1100
CLK 35
CLOCK
BUFFER
CKE 34
CONTROL COLUMN DECODER
CS 18
SIGNAL
R
RAS 17 O
GENERATOR
COMMAND W
CAS 16 DECODER
D CELL ARRAY
2 DQ0
E BANK #0
WE 15
C
3 DQ1
O
D
E 5 DQ2
R
A10 20
6 DQ3
SENSE AMPLIFIER
8 DQ4
9 DQ5
MODE 11 DQ6
A0 21
REGISTER
12 DQ7
A3 24 ADDRESS
REFRESH DQ
BUFFER
A4 27 COUNTER BUFFER 39 DQ8
40 DQ9
A9 32
42 DQ10
BA 19
43 DQ11
45 DQ12
46 DQ13
REFRESH COLUMN
COLUMN DECODER 48 DQ14
COUNTER COUNTER
R
49 DQ15
O
W
D CELL ARRAY
E
BANK #1
C
O
D
E
14 LDQM
R
36 UDQM
SENSE AMPLIFIER
IC6: SN74AHC1G08DCKR
2-input positive-AND gate
A 1 5 Vcc
B 2
GND 3 4 Y
IC8: SN74LV245APWR
Octal bus transceivers with 3-state outputs
DIR 1 20 Vcc
A1 2 19 OE
A2 3 18 B1
A3 4 17 B2
A4 5 16 B3
A5 6 15 B4
7 14
A6 B5
A7 8 13 B6
A8 9 12 B7
GND 10 11 B8
DQ0–DQ15 (A- 1)
RY/ BY#
V
CC
Sect or Sw itc hes
V
SS
Erase V olt ag e
In put/ Out put
RESET#
Generat or Buff ers
WE# State
Contr ol
BYTE#
Comm and
Regi st er
PGM Vo ltage
Generator
Data
Chip Enab le
Out put Enable STB Lat ch
CE#
Logic
OE#
Y-Decoder
Y- Gating
STB
V De te ct or Tim er
CC
X- Decoder Cell M atrix
A0– A17
1CLR 1 14 VCC
Q
1D 2CLR
2 13
1CLK 3 12 2D
C
1PRE 4 11 2CLK
1Q 5 10 2PRE
TG 1Q 6 9 2Q
GND 7 8 2Q
Q
C
61